检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,804 篇 会议
185 篇 期刊文献
80 册 图书
1 篇 学位论文

馆藏范围

4,070 篇 电子文献
1 种 纸本馆藏

日期分布

学科分类号

2,090 篇 工学
- 1,905 篇 计算机科学与技术...
- 1,021 篇 软件工程
- 368 篇 电气工程
- 153 篇 信息与通信工程
- 138 篇 电子科学与技术（可...
- 75 篇 控制科学与工程
- 30 篇 机械工程
- 30 篇 生物工程
- 24 篇 材料科学与工程（可...
- 24 篇 生物医学工程（可授...
- 23 篇 仪器科学与技术
- 21 篇 光学工程
- 19 篇 建筑学
- 17 篇 测绘科学与技术
- 16 篇 土木工程
- 13 篇 动力工程及工程热...
- 12 篇 农业工程
526 篇 理学
- 416 篇 数学
- 51 篇 物理学
- 39 篇 系统科学
- 33 篇 生物学
- 29 篇 统计学（可授理学、...
- 16 篇 化学
- 16 篇 地球物理学
205 篇 管理学
- 153 篇 管理科学与工程(可...
- 61 篇 工商管理
- 53 篇 图书情报与档案管...
19 篇 农学
- 14 篇 作物学
18 篇 法学
- 18 篇 社会学
15 篇 经济学
- 15 篇 应用经济学
13 篇 医学
3 篇 文学
3 篇 军事学
2 篇 教育学
2 篇 艺术学
1 篇 哲学

主题

644 篇 parallel process...
544 篇 parallel program...
526 篇 computer archite...
463 篇 parallel archite...
448 篇 concurrent compu...
359 篇 parallel algorit...
319 篇 programming
313 篇 hardware
285 篇 computer science
276 篇 algorithm design...
263 篇 computational mo...
214 篇 programming prof...
165 篇 parallel process...
163 篇 dynamic programm...
154 篇 application soft...
138 篇 costs
137 篇 program processo...
137 篇 distributed comp...
134 篇 libraries
133 篇 runtime

机构

9 篇 stanford univ st...
9 篇 intel corporatio...
8 篇 oak ridge natl l...
8 篇 univ calif berke...
7 篇 school of comput...
7 篇 oak ridge nation...
7 篇 carnegie mellon ...
7 篇 college of compu...
7 篇 oak ridge nation...
7 篇 univ texas austi...
6 篇 school of comput...
6 篇 sandia national ...
6 篇 department of co...
6 篇 barcelona superc...
6 篇 department of co...
6 篇 school of comput...
6 篇 department of co...
5 篇 department of co...
5 篇 nvidia corporati...
5 篇 pacific northwes...

作者

15 篇 jack dongarra
12 篇 dongarra jack
11 篇 hong shen
10 篇 hoefler torsten
9 篇 zhong cheng
9 篇 olukotun kunle
9 篇 gu yan
8 篇 chapman barbara
7 篇 garcia i.
7 篇 forsell martti
7 篇 sun yihan
7 篇 jigang wu
7 篇 nakano koji
7 篇 danelutto marco
6 篇 cheng zhong
6 篇 v.k. prasanna
6 篇 blelloch guy e.
6 篇 h.j. siegel
6 篇 lumsdaine andrew
6 篇 tsigas philippas

语言

4,037 篇 英文
26 篇 其他
8 篇 中文

检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

共 4070 条记录，以下是3971-3980 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Adaptive parallel Interval Global Optimization algorithms Based on their Performance for Non-dedicated Multicore architectures

Adaptive Parallel Interval Global Optimization Algorithms Ba...

引用

Euromicro Conference on parallel, Distributed and Network-Based Processing

作者： J.F. Sanjuan Estrada L.G. Casado I. García Universidad de Almeria Almeria AndalucÃa ES Department of Computer Architecture and Electronics University of Almeria Almería Spain Department of Computer Architecture University of Mälaga Mälaga Spain

Branch and Bound (B&B) algorithms are highly parallelizable but they are irregular and dynamic load balancing techniques have been used to avoid idle processors. In previous work, authors use a dynamic number of threads at run time, which depends on the measured performance of the application for just one interval B&B algorithm running on the system. In this way, load balancing is achieved by thread generation decisions. In this work, we extend the study of these models to non-dedicated systems. In order to have a controlled test bed and comparable results, several instances of the interval global optimization algorithm are executed in the system, with the same model and problem to solve. Therefore, a non-dedicated system is simulated because the execution of one application affects the execution of the other instances. This paper discusses different methods and models to decide when a thread should be created. Experiments show which of the proposed methods performs best in terms of maximum running time per application, using the fewest running threads. Following this parallel programming methodology, which is well suited for other B&B codes, applications can adapt their parallelism level to their performance and load of the system(at run time). This work represents a step forward towards increasing the performance of parallel algorithm running in non-dedicated and heterogeneous systems. The adaptive model discussed in this work is able to reduce the overall execution time for a set of instances of the same application running simultaneously. It also exempts the user from specifying the number of threads each application should use.

关键词： Instruction sets Kernel Computational modeling Adaptation model Load modeling parallel processing

来源：评论

学校读者我要写书评

暂无评论

parallel Computing with GPU: An accelerator for Data-Centric High Performance Computing

Parallel Computing with GPU: An accelerator for Data-Centric...

引用

Innovative Engineering Sciences and Technological Research (ICIESTR), international Conference on

作者： Mohammed Siddique Mohammed Waleed Ashour Faculty of Information Technology Majan University College Muscat Oman

ISBN: (数字)9798350348637

ISBN: (纸本)9798350348644

In recent years, the demand for high-performance computing in various disciplines of ICTs has affected the dependency on single core processes due to its decline in efficiency. Whereas, this requirement of advance in processing power has seen the emergence of Graphical Processing Units (GPU). In this paper, the role of GPUs in parallel computing along with its advantages, limitations and performance in various domains have been presented. The massive parallelism feature of GPUs can break down complex problems into smaller bits of computation with greater efficiency. The ability to compute complex distributed processes is ideal for implementing Machine Learning (ML) and Deep Learning (DL) algorithms. The evaluation of GPUs performance in medical physics, large scale data mining, CUDA workload analysis and applications of ML and DL has been deliberated on the high-performance computing. As GPUs continue to evolve, processing performance and efficiency should improve, and stand out as a cost-effective and powerful solution for optimizing faster and reliable large-scale data processing. Future research is expected to optimize GPU architectures for developing computing paradigms to keep them relevant in high-performance computing's fast-changing industry.

关键词： Training Performance evaluation Tensors High performance computing Computational modeling Graphics processing units parallel processing programming Reliability Physics

来源：评论

学校读者我要写书评

暂无评论

Compiling Higher Order Functional Programs to Composable Digital Hardware

Compiling Higher Order Functional Programs to Composable Dig...

引用

Annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Eduardo Aguilar-Pelaez Samuel Bayliss Alex Smith Felix Winterstein Dan R. Ghica David Thomas George A. Constantinides Imperial College London London London GB Imperial College London London UK University of Birmingham Birmingham UK Ground Station Systems Division European Space Agency Darmstadt Germany

This work demonstrates the capabilities of a high-level synthesis tool-chain that allows the compilation of higher order functional programs to gate-level hardware descriptions. Higher order programming allows functions to take functions as parameters. In a hardware context, the latency-insensitive interfaces generated between compiled modules enable late-binding with libraries of pre-existing functions at the place-and-route compilation stage. We demonstrate the completeness and utility of our approach using a case study; a recursive k-means clustering algorithm. The algorithm features complex data-dependent control flow and opportunities to exploit both coarse and fine-grained parallelism.

关键词： Hardware programming Field programmable gate arrays Educational institutions Clustering algorithms parallel processing Program processors

来源：评论

学校读者我要写书评

暂无评论

A regular parallel RSA processor

A regular parallel RSA processor

引用

Midwest symposium on Circuits and Systems (MWSCAS)

作者： Qiang Liu Fangzhen Ma Dong Tong Xu Cheng The Department of Computer Science and Technology Peking University Beijing China School of Information Management University of International Business and Economics Beijing China

ISBN: (纸本)078038346X

High performance VLSI implementation of the RSA algorithm using the systolic array is presented. High-speed applications of RSA systems require parallel implementations of modular multipliers. Besides using the systolic architecture which is popular in hardware-based RSA systems, a block-based scheme is used to further eliminate global signals, with a pipelined bus to convey data globally. The control signals and intermediate results used for sequential multiplications are transmitted by shift registers. All signals, except for the clock signal, are limited in one block or between two adjacent blocks. A carry-save-adder structure is used for calculating the iterative step of the algorithm, which contributes to speed improvement and area saving. In addition, long modular multipliers suffer from the effect of large fanout. Novel architectures are proposed to eliminate the fanout bottleneck, which reduce the achievable minimum clock period of long modular multipliers. Compared to the original modular multiplier architecture with fanout bottleneck, the proposed architectures can achieve an increase of over 7% in throughput without increase in area. The Chinese remainder theorem (CRT) technique increases the decryption data rate by a factor of four. Two redundant blocks are added to adapt to the on-line partition of the multiplier and the variation of the length of P and Q in CRT mode.

关键词： Broadcasting Systolic arrays Clocks Shift registers Iterative algorithms Cathode ray tubes Security Delay Computer science Very large scale integration

来源：评论

学校读者我要写书评

暂无评论

A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration

A Coarse Grained Reconfigurable Architecture for SHA-2 Accel...

引用

IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Hoai Luan Pham Thi Hong Tranl Vu Trung Duong Le Yasuhiko Nakashima Nara Institute of Science and Technology Nara Japan Osaka City University Osaka Japan

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The development of high-speed SHA-2 hardware with high flexibility is urgently needed because SHA-2 functions are widely employed in numerous fields, from loT devices to cryp-to currency. Unfortunately, the existing SHA-2 circuits have difficulty in achieving high flexibility and hardware efficiency. Therefore, this paper proposes a coarse-grained reconfigurable architecture (CGRA) for accelerating SHA-2 computation, named a CGRA SHA-2 accelerator. To effectively support various algorithms and requirements, three optimization techniques are proposed to achieve high flexibility and hardware efficiency. First, an on-demand pro-cessing element array is proposed to enable flexible computation for long and short messages. Second, a dual-ALU processing element (D-PE) is proposed to compute various SHA-2 functions. Third, the pipelined dual-ALU architecture is proposed to reduce the critical paths, leading to remarkably improved performance and hardware efficiency. The accuracy of our proposed accelerator is verified on a real hardware platform (the Xilinx Alveo U280 FPGA). Besides, the experimental results on several FPGAs prove that the proposed CGRA SHA-2 accelerator is significantly higher performance, hardware efficiency, and flexibility than existing works.

关键词： Power demand Graphics processing units parallel processing Network security Throughput Hardware Reconfigurable architectures

来源：评论

学校读者我要写书评

暂无评论

ABARIS: An Adaptable Fault Detection/Recovery Component Framework for MPIs

ABARIS: An Adaptable Fault Detection/Recovery Component Fram...

引用

international symposium on parallel and Distributed Processing (IPDPS)

作者： Hideyuki Jitsumoto Toshio Endo Satoshi Matsuoka Tokyo Institute of Technology Tokyo Japan National Institute of Information Chiyoda Tokyo Japan

Long-running MPI applications on clusters and grids that are prone to node and network failures, motivates the use of fault tolerant MPI implementations. However, previous fault tolerant MPIs lack the ability to allow the user to easily choose appropriate fault recovery strategies according to the execution environment, independent of the application codes-rather, the user often had to hard-code restoration strategies in accordance to diverse sets of fault patterns, which could be numerous: for instance, if the fault is transient to a particular process, we merely have to restart the process on the same computing node; on the other hand, if the fault is due to repetitive hardware unreliability, we must migrate the process to a new node in its recovery. ABARIS is our new fault/recovery model aware component framework for MPI, where users can customize MPI fault detection and recovery algorithms according to their application and execution environmental requirements by merely selecting appropriate fault/recovery components, independent of the application code. Currently, the ARABIS framework prototype is implemented on top of MPICH-P4MPD. Preliminary evaluation of the prototype using NPB on our MPI fault simulator demonstrates that overhead compared to the original MPICH-P4MPD is almost negligible (less than 1%) under normal execution, and when faults occur, appropriate selections and pairings of fault model and recovery method components for corresponding to the execution environment is significant to the overall execution time.

关键词： Fault detection Object oriented modeling Fault tolerance programming profession Protocols Hardware Switches Prototypes Virtual prototyping Informatics

来源：评论

学校读者我要写书评

暂无评论

Virtual Machine Scheduling for parallel Soft Real-Time Applications

Virtual Machine Scheduling for Parallel Soft Real-Time Appli...

引用

international symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Like Zhou Song Wu Huahua Sun Hai Jin Xuanhua Shi Services Computing Technology and System Lab Huazhong University of Science and Technology Wuhan China

With the prevalence of multicore processors in computer systems, many soft real-time applications, such as media-based ones, use parallel programming models to utilize hardware resources better and possibly shorten response time. Meanwhile, virtualization technology is widely used in cloud data centers. More and more cloud services including such parallel soft real-time applications are running in virtualized environment. However, current hyper visors do not provide adequate support for them because of soft real-time constraints and synchronization problems, which result in frequent deadline misses and serious performance degradation. CPU schedulers in underlying hyper visors are central to these issues. In this paper, we identify and analyze CPU scheduling problems in hyper visors, and propose a novel scheduling algorithm considering both soft real-time constraints and synchronization problems. In our proposed method, real-time priority is introduced to accelerate event processing of parallel soft real-time applications, and dynamic time slice is used to schedule virtual CPUs. Besides, all runnable virtual CPUs of virtual machines running parallel soft real-time applications are scheduled simultaneously to address synchronization problems. We implement a parallel soft real-time scheduler, named Poris, based on Xen. Our evaluation shows Poris can significantly improve the performance of parallel soft real-time applications. For example, compared to the Credit scheduler, Poris improves the performance of media player by up to a factor of 1.35, and shortens the execution time of PARSEC benchmark by up to 44.12%.

关键词： Real-time systems Synchronization Schedules Scheduling Time factors Scheduling algorithms Virtual machine monitors

来源：评论

学校读者我要写书评

暂无评论

Predicting indirect branches via data compression

Predicting indirect branches via data compression

引用

IEEE/ACM international symposium on Microarchitecture (MICRO)

作者： J. Kalamatianos D.R. Kaeli Department of Electrical and Computer Engineering Northeastern University Boston MA USA

Branch prediction is a key mechanism used to achieve high performance on multiple issue, deeply pipelined processors. By predicting the branch outcome at the instruction fetch stage of the pipeline, superscalar processors become able to exploit Instruction Level parallelism (ILP) by providing a larger window of instructions. However, when a branch is mispredicted, instructions from the mispredicted path must be discarded. Therefore, branch prediction accuracy is critical to achieve high performance. Existing branch prediction schemes can accurately predict the direction of conditional branches, but have difficulties predicting the correct targets of indirect branches. Indirect branches occur frequently in Object-Oriented Languages (OOL), as well as in Dynamically-Linked Libraries (DLLs), two programming environments rapidly increasing in popularity. In addition, certain language constructs such as multi-way control transfers (e.g., switches), and architectural features such as 64-bit address spaces, utilize indirect branching. In this paper, we describe a new algorithm for predicting unconditional indirect branches called Prediction by Partial Matching (PPM). We base our approach on techniques proven to work optimally in the field of data compression. We combine a viable implementation of the PPM algorithm with dynamic per-branch selection of path-based correlation and compare its prediction accuracy against a variety of predictors. Our results show that, for approximately the same hardware budget, the combined predictor can achieve a misprediction ratio of 9.47%, as compared to 11.48% for the previously published most accurate indirect branch predictor.

关键词： Data compression Accuracy Pipelines parallel processing Libraries programming environments Switches Electronic switching systems Prediction algorithms Heuristic algorithms

来源：评论

学校读者我要写书评

暂无评论

Application Modeling for Scalable Simulation of Massively parallel Systems

Application Modeling for Scalable Simulation of Massively Pa...

引用

IEEE international Conference on High Performance Computing and Communications (HPCC)

作者： Eric Anger Damian Dechev Gilbert Hendry Jeremiah Wilke Sudhakar Yalamanchili Georgia Institute of Technology Atlanta Georgia University of Central Florida Orlando Florida Sandia National Laboratories Livermore California

Macro-scale simulation has been advanced as one tool for application -- architecture co-design to express operation of exascale systems. These simulations approximate the behavior of system components, trading off accuracy for increased evaluation speed. Application skeletons serve as the vehicle for these simulations, but they require accurately capturing the execution behavior of computation. The complexity of application codes, the heterogeneity of the platforms, and the increasing importance of simulating multiple performance metrics (e.g., execution time, energy) require new modeling techniques. We propose flexible statistical models to increase the fidelity of application simulation at scale. We present performance model validation for several exascale mini-applications that leverage a variety of parallel programming frameworks targeting heterogeneous architectures for both time and energy performance metrics. When paired with these statistical models, application skeletons were simulated on average 12.5 times faster than the original application incurring only 6.08% error, which is 12.5% faster and 33.7% more accurate than baseline models.

关键词： Computational modeling Skeleton Analytical models Load modeling Hardware Predictive models Data models

来源：评论

学校读者我要写书评

暂无评论

Energy Saving in Distributed Router architectures

Energy Saving in Distributed Router Architectures

引用

IEEE international Conference on Communications

作者： Andrea Bianco Fikru Getachew Debele Luca Giraudo Dipartimento di Elettronica e delle Telecomunicazioni Politecnico di Torino

ISBN: (纸本)9781457720529

A multi-stage software router overcomes scalability issues related to a single, PC-based, software router by introducing parallel forwarding paths. However, since the architecture includes different internal components, energy inefficiency at low loads may arise if the multi-stage internal architecture does not adapt to currently offered traffic. This paper presents an energy-saving scheme to improve energy efficiency of the multi-stage router architecture by focusing on the back-end stage and sizing it to the offered load to reduce energy needs. The problem is defined as a mixed integer linear programming model, shown to be NP-hard. We tackle the scalability issues of the optimal problem by defining a two-step heuristic which takes advantage of existing BIN PACKING algorithms. Our results shows that the two-step solution is within 10% relative error with respect to the optimal solution for different realistic scenarios.

关键词： ARCHITECTURE Mixed integer linear programming relative errors energy saving Building construction Energy conservation Scalability Nondeterministic polynomial-time hard optimal solution Energy sources offered traffic Energy efficiency Bins LOAD

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共407页 << < 394 395 396 397 398 399 400 401 402 403 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：