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Automatic generation and configuration of Wireless Sensor Networks applications with Genetic programming

Automatic generation and configuration of Wireless Sensor Ne...

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international symposium on Object-Oriented Real-Time Distributed Computing

作者： Tales Heimfarth Renato Resende Ribeiro de Oliveira Raphael Winckler de Bettio Ariel Felipe Ferreira Marques Claudio Fabiano Motta Toledo Universidade Federal de Lavras Lavras Minas Gerais Brazil Universidade Federal de Lavras Lavras MG BR Institute of Mathematical and Computer Sciences Universidade de Sao Paulo Sao Paulo SÃ£o Paulo BR

The development of Wireless Sensor Networks (WSNs) applications is an arduous task, since the developer has to design the behavior of the nodes and their interactions. The automatic generation of WSN's applications is desirable to reduce costs, since it drastically reduces the human effort. This paper presents the use of Genetic programming to automatically generate WSNs applications. A scripting language based on events and actions is proposed to represent the WSN behavior. Events represent the state of a given sensor node and actions modify these states. Some events are internal states and others are external states captured by the sensors. A parallel genetic algorithm is used to automatically generate WSNs applications in this scripting language. These scripts are executed by a middleware installed on all sensors nodes. This approach enables the application designer to define only the overall objective of the WSN. This objective is defined by means of a fitness function. An event-detection problem is presented in order to evaluate the proposed method. The results showed the capability of the developed approach to successfully solve WSNs problems through the automatic generation of applications.

关键词： Wireless sensor networks Genetic algorithms Middleware Sociology Statistics Virtual machining Genetic programming

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parallel Optimization of Spaceborne SAR Echo Simulation and Imaging Using OpenCL Based on GPGPU

Parallel Optimization of Spaceborne SAR Echo Simulation and ...

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IEEE international symposium on Geoscience and Remote Sensing (IGARSS)

作者： Fanle Meng Fei Ma Fan Zhang College of Information Science and Technology Beijing University of Chemical Technology Beijing China

ISBN: (数字)9798350360325

ISBN: (纸本)9798350360332

A ground-based simulation system is necessary to verify the feasibility of real spaceborne Synthetic Aperture Radar (SAR) systems. Since echo simulation and image generation are computationally complex, parallel acceleration for SAR systems has been an active research area. However, most of the acceleration algorithms utilize compute unified device architecture (CUDA) as the programming platform, that works only on NVIDIA’s GPUs. This paper proposes a parallel optimization algorithm for spaceborne SAR echo simulation and imaging in Open Computing Language (OpenCL). In the echo simulation module, we optimize the Fast Fourier Transform (FFT), the calculation of range echoes, and the synchronization operation. In the imaging module, the data is decomposed to reduce the computational burden, and matrix transpose and phase factor multiplication are optimized using OpenCL. The architecture and steps needed to extract parallelism in the implementation of the algorithm for accelerated SAR echo simulation and imaging are described in detail. Benefiting from the better generality of OpenCL, this algorithm can be used to program General-Purpose Graphics Processing Units (GPGPU), i.e., CPUs, GPUs, and other types of processors. The performance is promoted by orders of magnitude compared with CPU-based implementation.

关键词： Fast Fourier transforms Spaceborne radar Imaging Graphics processing units Computer architecture Radar polarimetry Synchronization

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On the Development of Variable Size Batched Computation for Heterogeneous parallel architectures

On the Development of Variable Size Batched Computation for ...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Ahmad Abdelfattah Azzam Haidar Stanimire Tomov Jack Dongarra Innovative Computing Laboratory University of Tennessee Knoxville TN USA University of Manchester Manchester UK Oak Ridge National Laboratory Oak Ridge TN USA

ISBN: (纸本)9781509036837

Many scientific applications, ranging from national security to medical advances, require solving a number of relatively small-size independent problems. As the size of each individual problem does not provide sufficient parallelism for the underlying hardware, especially accelerators, these problems must be solved concurrently as a batch in order to saturate the hardware with enough work, hence the name batched computation. A possible simplification is to assume a uniform size for all problems. However, real applications do not necessarily satisfy such assumption. Consequently, an efficient solution for variable-size batched computations is required. This paper proposes a foundation for high performance variable-size batched matrix computation based on Graphics Processing Units (GPUs). Being throughput-oriented processors, GPUs favor regular computation and less divergence among threads, in order to achieve high performance. Therefore, the development of high performance numerical software for this kind of problems is challenging. As a case study, we developed efficient batched Cholesky factorization algorithms for relatively small matrices of different sizes. However, most of the strategies and the software developed, and in particular a set of variable size batched BLAS kernels, can be used in many other dense matrix factorizations, large scale sparse direct multifrontal solvers, and applications. We propose new interfaces and mechanisms to handle the irregular computation pattern on the GPU. According to the authors' knowledge, this is the first attempt to develop high performance software for this class of problems. Using a K40c GPU, our performance tests show speedups of up to 2.5x against two Sandy Bridge CPUs (8-core each) running Intel MKL library.

关键词： Kernel Graphics processing units Libraries Multicore processing Hardware Instruction sets

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A Fast Approximate String Matching Algorithm on GPU

A Fast Approximate String Matching Algorithm on GPU

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international symposium on Computing and Networking (CANDAR)

作者： Lucas S.N. Nunes Jacir L. Bordim Koji Nakano Yasuaki Ito Department of Computer Science University of Brasília Brasília DF Brazil Department of Information Engineering Hiroshima University Higashi-Hiroshima Japan

The approximate string matching (ASM) problem asks to find a substring of string Y of length n that is most similar to string X of length m. The ASM can be solved by dynamic programming technique, which computes a table of size m × n. The main contribution of this work is to present a memory-access-efficient implementation for computing the ASM on a GPU. The key idea of our implementation relies on warp shuffle for communication between threads without resorting to shared memory access. Surprisingly, our implementation performs only O(mn/w) memory access operations, where w is the warp size, although O(mn) memory access operations are necessary to access all elements in the table of size n × m. Experimental results, carried out on a GeForce GTX 980 GPU, shows that the proposed implementation called w-SCAN provides a speed-up factor over 200 as compared to a single CPU implementation. Also, w-SCAN computes the ASM in less than 40% of the time required by another prominent alternative.

关键词： Graphics processing units Instruction sets Hidden Markov models Approximation algorithms Memory management Acceleration parallel algorithms

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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only) 10

Design space exploration of throughput-optimized arrays from...

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Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

作者： Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Washington University in St. Louis St. Louis MO USA

ISBN: (纸本)9781605589114

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. These architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

关键词： dynamic programming systolic array throughput optimization fpga recurrences

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Lock-free Computation of PageRank in Dynamic Graphs

Lock-free Computation of PageRank in Dynamic Graphs

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Subhajit Sahu Kishore Kothapalli Hemalatha Eedi Sathya Peri International Institute of Information Technology Hyderabad India JNTUH College of Engineering Hyderabad India Indian Institute of Technology Hyderabad India

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

PageRank is a metric that assigns importance to the vertices of a graph based on its neighbors and their scores. Recently, there has been increasing interest in computing PageRank on dynamic graphs, where the graph structure evolves due to edge insertions and deletions. However, traditional barrier-based approaches for updating PageRanks encounter significant wait times on certain graph structures, leading to high overall runtimes. Additionally, the growing trend of multicore architectures with increased core counts has raised concerns about random thread delays and failures. In this study, we propose a lock-free algorithm for updating PageRank scores on dynamic graphs. First, we introduce our Dynamic Frontier (DF) approach, which identifies and processes vertices likely to change PageRanks with minimal overhead. Subsequently, we integrate DF with our lock-free and fault-tolerant PageRank (Alg. DF LF ), incorporating a helping mechanism among threads between its two phases. Experimental results demonstrate that Alg. DF LF not only eliminates waiting times at iteration barriers but also withstands random thread delays and crashes. On average, it is 4.6× faster than lock-free Naive-dynamic PageRank (Alg. ND LF ).

关键词： Measurement Runtime Multicore processing Instruction sets Heuristic algorithms Redundancy Fault tolerant systems

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REAL-TIME MUTUAL-INFORMATION-BASED LINEAR REGISTRATION ON THE CELL BROADBAND ENGINE PROCESSOR

REAL-TIME MUTUAL-INFORMATION-BASED LINEAR REGISTRATION ON TH...

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IEEE international symposium on Biomedical Imaging

作者： Moriyoshi Ohara Hangu Yeo Frank Savino Giridharan Iyengar Leiguang Gong Hiroshi Inoue Hideaki Komatsu Vadim Sheinin Shahrokh Daijavad Bradley Erickson IBM Tokyo Research Laboratory Kanagawa Yamato Japan IBM T.J. Watson Research Center Yorktown Heights NY USA IBM T.J. Watson Research Center Hawthorne NY USA IBM Systems & Technology Group Hawthorne NY USA Mayo Clinic and Foundation Rochester Minnesota USA

ISBN: (纸本)9781424406715

Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-information-based 3D linear registration algorithm on the Cell Broadband Enginetrade (CBE) processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core. By exploiting the highly parallel architecture and its high memory bandwidth, our implementation with two CBE processors can compute mutual information for about 33 million pixel pairs in a second. This implementation is significantly faster than a conventional one on a traditional microprocessor or even faster than a previously reported custom-hardware implementation. As a result, it can register a pair of 256times256times30 3D images in one second by using a multi-resolution method. This paper describes our implementation with a focus on localized sampling and speculative packing techniques, which reduce the amount of the memory traffic by 82%

关键词： Engines Multicore processing Acceleration Biomedical imaging parallel processing parallel architectures Bandwidth Concurrent computing Mutual information Microprocessors

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A Framework for Modular Signal Processing Systems with High-Performance Requirements

A Framework for Modular Signal Processing Systems with High-...

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IEEE international Conference on Multimedia and Expo (ICME)

作者： Lukas Diduch Ronald Muller Gerhard Rigoll Information Access Division National Institute for Standards and Technology Gaithersburg MD USA Institute for Human-Machine Communication Technische Universität München Germany

This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our C/C++ framework is designed to constitute the basis of a well organized and simplified development process in industrial and academic research teams. It supports the structuring of modular systems by provision of basic data-, parameter-, and command-interfaces, ensuring the re-usability of the system components. Due to the underlying multi-threading capabilities, the applications built in MMER Lab are enabled to fully exploit the increasing computational power of multi-core CPU architectures. This feature is carried out by a buffering concept which controls the data flow between the connected modules and allows for the parallel processing of consecutive signal segments (e.g. video frames). We introduce the concept of the multi-threading environment and the data flow architecture with its comfortable programming interface. We illustrate the proposed module concept for the generic assembly of processing chains and show applications from the area of video analysis and pattern

关键词： Signal processing Signal processing algorithms Graphical user interfaces Computer architecture Communication cables Software performance parallel processing Application software Yarn Communication system software

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A GPU-enabled solver for time-constrained linear sum assignment problems

A GPU-enabled solver for time-constrained linear sum assignm...

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The international Conference on Informatics and Systems (INFOS)

作者： Roberto Roverso Amgad Naiem Mohammed El-Beltagy Sameh El-Ansary Seif Haridi KTH Royal Institute of Technology Sweden Cairo University Egypt Nile University Egypt

ISBN: (纸本)9781424458288;9789774033964

This paper deals with solving large instances of the Linear Sum Assignment Problems (LSAPs) under realtime constraints, using Graphical Processing Units (GPUs). The motivating scenario is an industrial application for P2P live streaming that is moderated by a central tracker that is periodically solving LSAP instances to optimize the connectivity of thousands of peers. However, our findings are generic enough to be applied in other contexts. Our main contribution is a parallel version of a heuristic algorithm called Deep Greedy Switching (DGS) on GPUs using the CUDA programming language. DGS sacrifices absolute optimality in favor of a substantial speedup in comparison to classical LSAP solvers like the Hungarian and auctioning methods. We show the modifications needed to parallelize the DGS algorithm and the performance gains of our approach compared to a sequential CPU-based implementation of DGS and a mixed CPU/GPU-based implementation of it.

关键词： Computer languages Peer to peer computing parallel architectures Best practices Application software Paper technology Heuristic algorithms Performance gain Central Processing Unit Large-scale systems

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parallel algorithms and architectures for rule-based systems 86

Parallel algorithms and architectures for rule-based systems

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Proceedings of the 13th annual international symposium on Computer architecture

作者： A. Gupta C. Forgy A. Newell R. Wedig Carnegie-Mellon UniversityPittsburgh Pennsylvania

ISBN: (纸本)9780818607196

Rule-based systems, on the surface, appear to be capable of exploiting large amounts of parallelism—it is possible to match each rule to the data memory in parallel. In practice, however, we show that the speed-up from parallelism is quite limited, less than 10-fold. The reasons for the small speed-up are: (1) the small number of rules relevant to each change to data memory; (2) the large variation in the processing required by the relevant rules; and (3) the small number of changes made to data memory between synchronization steps. Furthermore, we observe that to obtain this limited factor of 10-fold speed-up, it is necessary to exploit parallelism at a very fine granularity. We propose that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/sec. This speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.

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