检索结果-内蒙古大学图书馆

IEEE international Conference on Robotics and Automation (ICRA)

作者： T. Gross H. Kung M. Lam J. Webb Department of Computer Science Carnegie-Mellon University Pittsburgh PA

Warp is a programmable systolic array processor. One of its objectives is to support computer vision research. This paper shows how the Warp architecture can be used to fulfill the computational needs of low-level vision. We study the characteristics of low-level vision algorithms and show how they lead to requirements for computer architecture. These requirements are met by Warp. We then describe how the Warp system can be used. Warp programs can be classified in two ways: chained versus severed, and heterogeneous versus homogeneous. Chained and severed characterize the degree of interprocessor dependency, while heterogeneous and homogeneous characterize the degree of similarity between programs on individual processors. Taken in combination, these classes give four user models. Sophisticated programming tools are needed to support these user models.

关键词： Systolic arrays Computer architecture Application software Computer vision Contracts parallel architectures Image processing Computer science Machine vision Displays

来源：评论

学校读者我要写书评

暂无评论

The Dataflow Abstract Machine Simulator Framework

The Dataflow Abstract Machine Simulator Framework

引用

Annual international symposium on Computer Architecture, ISCA

作者： Nathan Zhang Rubens Lacouture Gina Sohn Paul Mure Qizheng Zhang Fredrik Kjolstad Kunle Olukotun Stanford University Stanford USA MIT Cambridge USA

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

The growing interest in novel dataflow architectures and streaming execution paradigms has created the need for a simulator optimized for modeling dataflow systems. To fill this need, we present three new techniques that make it feasible to simulate complex systems consisting of thousands of components. First, we introduce an interface based on Communicating Sequential Processes which allows users to simultaneously describe functional and timing characteristics. Second, we introduce a scalable point-to-point synchronization scheme that avoids global synchronization. Finally, we demonstrate a technique to exploit slack in the simulated system, such as FIFOs, to increase simulation parallelism. We implement these techniques in the Dataflow Machine (DAM), a parallel simulator framework for dataflow systems. We demonstrate the benefits of using DAM by highlighting three case studies using the framework. First, we use DAM directly as an exploration tool for streaming algorithms on dataflow hardware. We simulate two different implementations of the attention algorithm used in large language models, and use DAM to show that the second implementation only requires a constant amount of local memory. Second, we re-implement a simulator for a sparse tensor algebra accelerator, resulting in $57 \%$ less code and a simulation speedup of up to four orders of magnitude. Finally, we demonstrate a general technique for time-multiplexing real hardware to simulate multiple virtual copies of the hardware using DAM.

关键词： Tensors Machine learning algorithms Dams Large language models Memory management Machine learning parallel processing

来源：评论

学校读者我要写书评

暂无评论

Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study

Compiler and Hardware Support for Cache Coherence in Large-S...

引用

Annual international symposium on Computer Architecture, ISCA

作者： Pen-Chung Yew L. Choi Center for Supercomputing Research and Development University of Illinois Urbana-Champaign Urbana-Champaign IL USA Department of Computer Science University of Minnesota Minneapolis MN USA

In this paper, we study a hardware-supported, compiler directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors, such as the Cray T3D. It can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is small and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data-flow analysis, have been implemented on the Polaris compiler [17].From our simulation study using the Perfect Club benchmarks, we found that, in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. With its comparable performance and reduced hardware cost, the scheme can be a viable alternative for large-scale multiprocessors, such as the Cray T3D, that rely on users to maintain data coherence.

关键词： Hardware Large-scale systems programming profession Data analysis Algorithm design and analysis Polarization Analytical models Performance analysis Multiprocessing systems Computer science

来源：评论

学校读者我要写书评

暂无评论

A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

A data-flow graph generation algorithm for a coarse-grained ...

引用

international Conference on ASIC

作者： Chao Yang Shouyi Yin Leibo Liu Shaojun Wei Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics Tsinghua University Beijing China Tsinghua University Beijing Beijing CN

In this paper, we present a C-to-DFG generation algorithm for coarse-grained reconfigurable processor in multimedia application field. The algorithm exploits the operation parallelism available in the sequential code; maximizes parallelism by loop unrolling and scalar replacement. Loop unrolling increases the size of basic block and fully exposes the intrinsic data parallelism. Scalar replacement eliminates memory access instructions from the basic block under the prerequisite condition of keeping data dependency. For mapping kernels, the three parts of DFGs are corresponding to the three sub-components of reconfigurable unit. The experiments evaluating the degrees of parallelism on DFGs suggest 5.2x to 120.4x speedups on four kernels from common multimedia algorithms.

关键词： Hardware parallel processing Computer languages Kernel programming profession Chaos Embedded computing High level languages Reconfigurable architectures Bridges

来源：评论

学校读者我要写书评

暂无评论

Automatic generation of fast BLAS3-GEMM: A portable compiler approach 17

Automatic generation of fast BLAS3-GEMM: A portable compiler...

引用

international symposium on Code Generation and Optimization (CGO)

作者： Xing Su Xiangke Liao Jingling Xue College of Computer National Laboratory for Parallel and Distributed Processing Changsha China UNSW School of Computer Science and Engineering Sydney NSW Australia

ISBN: (纸本)9781509049318

GEMM is the main computational kernel in BLAS3. Its micro-kernel is either hand-crafted in assembly code or generated from C code by general-purpose compilers (guided by architecture-specific directives or auto-tuning). Therefore, either performance or portability suffers. We present a POrtable Compiler Approach, Poca, implemented in LLVM, to automatically generate and optimize this micro-kernel in an architecture-independent manner, without involving domain experts. The key insight is to leverage a wide range of architecture-specific abstractions already available in LLVM, by first generating a vectorized micro-kernel in the architecture-independent LLVM IR and then improving its performance by applying a series of domain-specific yet architecture-independent optimizations. The optimized micro-kernel drops easily in existing GEMM frameworks such as BLIS and OpenBLAS. Validation focuses on optimizing GEMM in double precision on two architectures. On Intel Sandybridge and AArch64 Cortex-A57, Poca's micro-kernels outperform expert-crafted assembly code by 2.35% and 7.54%, respectively, and both BLIS and OpenBLAS achieve competitive or better performance once their micro-kernels are replaced by Poca's.

关键词： Kernel Optimization Computer architecture Linear algebra Libraries programming Program processors

来源：评论

学校读者我要写书评

暂无评论

Harvest rate of reconfigurable pipelines

Harvest rate of reconfigurable pipelines

引用

IEEE international symposium on Defect and Fault Tolerance in VLSI Systems

作者： Weiping Shi Ming-Feng Chang W. Kent Fuchs Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Information Engineering National Chiao Tung University Taiwan

Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.< >

关键词： Pipelines Wires Lattices Very large scale integration Switches Algorithm design and analysis parallel architectures Supercomputers Equations Engineering management

来源：评论

学校读者我要写书评

暂无评论

Implementing a reconfigurable atomic memory service for dynamic networks

Implementing a reconfigurable atomic memory service for dyna...

引用

international symposium on parallel and Distributed Processing (IPDPS)

作者： P.M. Musial A.A. Shvartsman Department of Computer Science and Engineering University of Connecticut Storrs CT USA Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Cambridge MA USA

Summary form only given. Transforming abstract algorithm specifications into executable code is an error-prone process in the absence of sophisticated compilers that can automatically translate such specifications into the target distributed system. We present a framework that was developed for translating algorithms specified as Input/Output Automata (IOA) to distributed programs. The framework consists of a methodology that guides the software development process and a core set of functions needed in target implementations that reduce unnecessary software development. The systems developed using this methodology preserve the modularity of the original specifications, making it easier to track refinements and effect optimizations. As a proof of concept, this work also presents a distributed implementation of a reconfigurable atomic memory service for dynamic networks (RAMBO). This service emulates atomic read/write shared objects in the dynamic setting where processors can arbitrarily crash, or join and leave the computation. The algorithm tolerates processor crashes and message loss and guarantees atomicity for arbitrary patterns of asynchrony and failure. The algorithm implementing the service is given in terms of IOA. An important consideration in formulating RAMBO was that it could be employed as a building block in real systems. Following a formal presentation of RAMBO algorithm, this work describes an optimized implementation that was developed using the methodology presented here. The system is implemented in Java and runs on a network of workstations. Empirical data illustrates the behavior of the system.

关键词： Computer science Automata programming Middleware Random access memory Artificial intelligence Laboratories Computer errors Computer crashes Java

来源：评论

学校读者我要写书评

暂无评论

Parla: A Python Orchestration System for Heterogeneous architectures

Parla: A Python Orchestration System for Heterogeneous Archi...

引用

Supercomputing Conference

作者： Hochan Lee William Ruys Ian Henriksen Arthur Peters Yineng Yan Sean Stephens Bozhi You Henrique Fingler Martin Burtscher Milos Gligoric Karl Schulz Keshav Pingali Christopher J. Rossbach Mattan Erez George Biros The University of Texas at Austin Austin TX USA Texas State University San Marcos TX USA

ISBN: (纸本)9781665454452

Python's ease of use and rich collection of numeric libraries make it an excellent choice for rapidly developing scientific applications. However, composing these libraries to take advantage of complex heterogeneous nodes is still difficult. To simplify writing multi-device code, we created Parla, a heterogeneous task-based programming framework that fully supports Python's scientific programming stack. Parla's API is based on Python decorators and allows users to wrap code in Parla tasks for parallel execution. Parla arrays enable automatic movement of data between devices. The Parla runtime handles resource-aware mapping, scheduling, and execution of tasks. Compared to other Python tasking systems, Parla is unique in its parallelization of tasks within a single process, its GPU context and resource-aware runtime, and its design around gradual adoption to provide easy migration of and integration into existing Python applications. We show that Parla can achieve performance competitive with hand-optimized code while improving ease of development.

关键词： Runtime Codes Scheduling algorithms parallel programming Prefetching High performance computing Writing

来源：评论

学校读者我要写书评

暂无评论

CONCEPTUAL: a network correctness and performance testing language

CONCEPTUAL: a network correctness and performance testing la...

引用

international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Pakin CCS-3: Modeling Algorithms and Informatics Group Computer and Computational Sciences (CCS) Division Los Alamos National Laboratory USA

Summary form only given. We introduce a new, domain-specific specification language called CONCEPTUAL. CONCEPTUAL enables the expression of sophisticated communication benchmarks and network validation tests in comparatively few lines of code. Besides helping programmers save time writing and debugging code, CONCEPTUAL addresses the important-but largely unrecognized-problem of benchmark opacity. Benchmark opacity refers to the current impracticality of presenting performance measurements in a manner that promotes reproducibility and independent evaluation of the results. For example, stating that a performance graph was produced by a "bandwidth" test says nothing about whether that test measures the data rate during a round-trip transmission or the average data rate over a number of back-to-back unidirectional messages; whether the benchmark preregisters buffers, sends warm-up messages, and/or preposts asynchronous receives before starting the clock; how many runs were performed and whether these were aggregated by taking the mean, median, or maximum; or, even whether a data unit such as "MB/s" indicates 10/sup 6/ or 2/sup 20/ bytes per second. Because CONCEPTUAL programs are terse, a benchmark's complete source code can be listed alongside performance results, making explicit all of the design decisions that went into the benchmark program. Because CONCEPTUAL's grammar is English-like, CONCEPTUAL programs can easily be understood by nonexperts. And because CONCEPTUAL is a high-level language, it can target a variety of messaging layers and networks, enabling fair and accurate performance comparisons.

关键词： Benchmark testing Specification languages programming profession Writing Debugging Measurement Reproducibility of results Bandwidth Clocks Performance evaluation

来源：评论

学校读者我要写书评

暂无评论

On supernode transformations and multithreading for the longest common subsequence problem

Conferences in Research and Practice in Information Technolo...

引用

Conferences in Research and Practice in Information Technology Series 2012年 127卷 3-12页

作者： Steinbrecher, Johann Shang, Weijia Santa Clara University 500 El Camino Real Santa Clara CA 95053 United States

ISBN: (纸本)9781921770081

The longest common subsequence (LCS) problem is an important algorithm in computer science with many applications such as DNA matching (bio-engineering) and file comparison (UNIX diff). While there has been a lot of research for finding an efficient solution to this problem, the research emphasis has shifted with the advent of multicore architectures towards multithreaded implementations. This paper applies supernode transformations to partition the dynamic programming solution of the LCS problem into multiple threads. Then, we enhance this method by presenting a transformation matrix that skews the loop nest such that loop carried dependencies of the inner loop are eliminated in each supernode. We find that this technique performs well on microarchitectures supporting out-oforder execution while in-order execution machines do not benefit from it. Furthermore, we present a variation of the supernode transformations and multithreading strategy which groups entire rows of the index set to form a supernode. The inter thread synchronization is performed by an array of mutexes. We find that this scheme reduces the amount of thread management overhead and improves the data locality. A formula for the total execution time of each method is presented. The techniques are benchmarked on a 12 core and a four core machine. At the 12 core machine the traditional supernode transformation speeds up the original loop nest 16:7 times. We enhance this technique to score a 42:6 speedup and apply our new method scoring a 59:5 speedup. We experience the phenomenon of superlinear speedup as the the performance gain is larger than the number of processing cores. Concepts presented and discussed in this paper on the LCS problem are generally applicable to regular dependence algorithms. © 2012, Australian Computer Society, Inc.

关键词： Dynamic programming

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：