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A Tropical Semiring Multiple Matrix-Product Library on GPUs: (not just) a step towards RNA-RNA Interaction Computations

A Tropical Semiring Multiple Matrix-Product Library on GPUs:...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Brandon Gildemaster Prerana Ghalsasi Sanjay Rajopadhye Department of Computer Science Colorado State University Fort Collins CO USA HP Enterprise Colorado Springs CO USA

ISBN: (数字)9781728174457

ISBN: (纸本)9781728174570

RNA-RNA interaction (RRI) is important in processes such as gene regulation, and certain classes of RRI are known to play roles in various diseases including cancer and Alzheimer's. Other classes are not as well studied but could have biological importance, thus there is a need for high-throughput tools which enable the study of these molecules. Current computational tools for RRI are slow: execution times in days, weeks or even months for large experiments, because the algorithms have time and space complexity, respectively O(N 3 M 3 ) and O(N 2 M 2 ), for two sequences length N and M. No GPU parallelization of such algorithms exists. We show how the most computationally expensive portion of RRI base pair maximization algorithms, an O(NM) 3 computation, can be expressed as O(N 3 ) instances of such matrix products. We therefore propose an optimized library for the core computation of BPMax, an RRI algorithm based on weighted base pair counting. Our library multiplies multiple pairs of matrices in the max-plus semiring. We explore multiple tradeoffs: a square matrix product library attains close to the machine peak, but does 6-fold unnecessary computations and has a 2× higher data footprint, while the one with the minimum work and memory footprint has thread divergence and unbalanced load. We also specialize for upper banded (trapezoidal shaped) matrices, which are relevant to a windowed version of the algorithm. STOP PRESS: just before we submitted the camera-ready version of the paper, we incorporated our library into a GPU implementation of the complete BPMax algorithm. We will report performance numbers at the workshop.

关键词： Heuristic algorithms RNA Rail to rail inputs Dynamic programming Libraries Graphics processing units Complexity theory

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Configurational optimizer of Combined Cycle Propulsion using Genetic programming

Configurational optimizer of Combined Cycle Propulsion using...

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IEEE symposium Series on Computational Intelligence

作者： Alessandro Mogavero Department of Mechanical and Aerospace engineering University of Strathclyde Glasgow UK G1 1XJ

ISBN: (纸本)9781509042418

In most engineering applications the optimization is employed after the conceptual design is already frozen with the only purpose of perfecting it. Although optimization algorithms capable of optimizing the configuration exist, their application is limited to electronics or control design, while for complex systems the conceptual design is often performed with manual trade off analyses among few options. In hypersonic propulsion for instance, the choice of which flow cycle to use is made mainly by means of experience or in the best case by a trade off between radically different architectures. For Combined Cycle Propulsion (CCP) however many flow cycle possibilities are available and it is very possible that the final design is influenced by the preconceptions of the engineers rather than a pure objective judgement. Therefore a configurational optimization process, not bound to any known configuration, can potentially deliver totally new engine concepts, aiding the creativity of the designer. In this paper the first steps toward a configurational optimization of CCP are shown. This optimization is intended to find the optimal engine design without knowing the engine conceptual design a-priori. The optimization algorithm is based on the Genetic programming (GP) and it was presented for the first time at the 20~(th)AIAA international Space Planes and Hypersonic Systems and Technologies Conference. In the present paper the fitness function has been improved with the addition of a constraint like penalty function designed to solve a convergence problem outlined in the previous version. The results presented in this paper demonstrate that the optimizer is able to converge to a reasonable configuration, coherent with the engineering practice. Moreover the improvements proposed in this paper proved to be effective in the mitigation of the previously detected problem, thus demonstrating that the optimization algorithm is robust and that the previous problems were only due t

关键词： optimizer Combined Cycle

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Architecture and programming of Analog In-Memory-Computing Accelerators for Deep Neural Networks

Architecture and Programming of Analog In-Memory-Computing A...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： HsinYu Sidney Tsai IBM

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Deep Neural Networks (DNNs) have demonstrated revolutionary capabilities in AI, such as machine vision, natural language processing, and content generation. However, the growing energy usage due to the excessive amount of data communication between compute and memory units highlights the need to address the “Von Neumann bottleneck.” In-memory computing can achieve high throughput and energy efficiency by computing multiply-accumulate (MAC) operations using Ohm's law and Kirchhoff's current law on arrays of resistive memory devices. In recent years, Analog non-volatile memory (NVM)- based accelerators with energy-efficient, weight-stationary MAC operations in analog NVM memoryarray “Tiles” have been demonstrated in hardware using Phase Change Memory (PCM) devices integrated in the backend of 14-nm CMOS. Based on the hardware demonstrations, we propose a highly heterogeneous and programmable accelerator architecture that takes advantage of a dense and efficient circuit-switched 2D mesh. This flexible architecture can accelerate Transformer, Long-Short-Term- Memory (LSTM), and Convolution Neural Networks (CNNs) while keeping data communication local and massively parallel. We show that by co-optimizing memory devices, DNN algorithms, and specialized digital circuits, competitive end-to-end DNN accuracies can be obtained with the help of hardware-aware training. The author would like to thank all colleagues at IBM Research Almaden, Yorktown, Albany NanoTech, Zurich, and Tokyo for their contributions to this work and the IBM Research AI HW Center.

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P-means, a parallel clustering algorithm for a heterogeneous multi-processor environment

P-means, a parallel clustering algorithm for a heterogeneous...

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international Conference on High Performance Computing & Simulation (HPCS)

作者： Aislan G. Foina Judit Planas Rosa M. Badia Francisco Javier Ramirez-Fernandez Barcelona Supercomputing Center and Artificial Intelligence Research Institute (IIIA) Spanish National Research Council (CSIC) Brazil Smart Sensors and Microsystems Group (SIM) Universidade de Sáo Paulo Brazil

G-means is a data mining clustering algorithm based on k-means, used to find the number of Gaussian distributions and their centers inside a multi-dimensional dataset. This paper presents the performance gain obtained from the development of a parallel G-means algorithm for a heterogeneous multi-processor environment using the StarSs framework, called here P means. The P-means execution was divided into 6 well defined steps, where each step was analyzed to create a hierarchical task structure in order to parallelize the execution enabling it to explore the hierarchy and heterogeneity of the Cell BE blades and others heterogeneous architectures. The algorithm implementation was also adapted to perform sequential timing measures to evaluate the Amdahl's law, to compare the theoretical calculation and the execution times' measurements and to introduce parallel computation by using the StarSs framework. The algorithm was executed using a 30 clusters dataset containing 600 thousand points of 60 dimensions in different hardware configurations in order to compare its execution time and speedup, and it showed a overall speedup of more than 18 times. A successful experimentation with real data demonstrated the usefulness of the algorithm.

关键词： Computer architecture Clustering algorithms Microprocessors Program processors Data mining programming Gaussian distribution

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Radiation-Induced Error Criticality in Modern HPC parallel Accelerators

Radiation-Induced Error Criticality in Modern HPC Parallel A...

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IEEE symposium on High-Performance Computer Architecture

作者： Daniel Alfonso Goncalves De Oliveira Laercio Lima Pilla Mauricio Hanzich Vinicius Fratin Fernando Fernandes Caio Lunardi José María Cela Philippe Olivier Alexandre Navaux Luigi Carro Paolo Rech Institute of Informatics UFRGS Porto Alegre Brazil Department of Informatics and Statistics UFSC Florianópolis Brazil CASE Department Barcelona Supercomputing Center Barcelona Spain

ISBN: (纸本)9781509049868

In this paper, we evaluate the error criticality of radiation-induced errors on modern High-Performance Computing (HPC) accelerators (Intel Xeon Phi and NVIDIA K40) through a dedicated set of metrics. We show that, as long as imprecise computing is concerned, the simple mismatch detection is not sufficient to evaluate and compare the radiation sensitivity of HPC devices and algorithms. Our analysis quantifies and qualifies radiation effects on applications' output correlating the number of corrupted elements with their spatial locality. Also, we provide the mean relative error (dataset-wise) to evaluate radiation-induced error magnitude. We apply the selected metrics to experimental results obtained in various radiation test campaigns for a total of more than 400 hours of beam time per device. The amount of data we gathered allows us to evaluate the error criticality of a representative set of algorithms from HPC suites. Additionally, based on the characteristics of the tested algorithms, we draw generic reliability conclusions for broader classes of codes. We show that arithmetic operations are less critical for the K40, while Xeon Phi is more reliable when executing particles interactions solved through Finite Difference Methods. Finally, iterative stencil operations seem the most reliable on both architectures.

关键词： Reliability Computer architecture Measurement Neutrons Resilience Computer crashes Supercomputers

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On Partitioning and Reordering Problems in a Hierarchically parallel Hybrid Linear Solver

On Partitioning and Reordering Problems in a Hierarchically ...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Ichitaro Yamazaki Xiaoye S. Li Francois-Henry Rouet Bora Uçar Electrical Engineering and Computer Science Department University of Tennessee Knoxville

PDSLin is a general-purpose algebraic parallel hybrid (direct/iterative) linear solver based on the Schur complement method. The most challenging step of the solver is the computation of a preconditioner based on the global Schur complement. Efficient parallel computation of the preconditioner gives rise to partitioning problems with sophisticated constraints and objectives. In this paper, we identify two such problems and propose hyper graph partitioning methods to address them. The first problem is to balance the work loads associated with different sub domains to compute the preconditioner. We first formulate an objective function and a set of constraints to model the preconditioner computation time. Then, to address these complex constraints, we propose a recursive hyper graph bisection method. The second problem is to improve the data locality during the parallel solution of a sparse triangular system with multiple sparse right-hand sides. We carefully analyze the objective function and show that it can be well approximated by a standard hyper graph partitioning method. Moreover, an ordering compatible with a post ordering of the sub domain elimination tree is shown to be very effective in preserving locality. To evaluate the two proposed methods in practice, we present experimental results using linear systems arising from some applications of our interest. First, we show that in comparison to a commonly-used nested graph dissection method, the proposed recursive hyper graph partitioning method reduces the preconditioner construction time, especially when the number of sub domains is moderate. This is the desired result since PDSLin is based on a two-level parallelization to keep the number of sub domains small by assigning multiple processors to each sub domain. We also show that our second proposed hyper graph method improves the data locality during the sparse triangular solution and reduces the solution time. Moreover, we show that partitioning time can be

关键词： Partitioning algorithms Sparse matrices Particle separators Standards Program processors Linear programming Algorithm design and analysis

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Runtime predictability of loops

Runtime predictability of loops

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IEEE international Workshop/symposium on Workload Characterization

作者： M.R. de Alba D.R. Kaeli Department of Electrical and Computer Engineering Northeastern University Boston MA USA

ISBN: (纸本)0780373154

To obtain the benefits of aggressive, wide-issue, architectures, a large window of valid instructions must be available. While researchers have been successful in obtaining high accuracies with a range of dynamic branch predictors, there still remains the need for more aggressive instruction delivery. Loop bodies possess a large amount of spatial and temporal locality. A large percentage of a program's entire execution can be attributed to code found in loop bodies. If we retain this code in a buffer or the cache, we do not have to refetch this code on subsequent loop iterations., Loops tend to iterate multiple times before exiting, thus providing us with the opportunity to speculatively issue multiple iterations. While some loops can be unrolled by a compiler many contain conditional branches. The number of times a loop iterates may be dependent on a program variable. These issues can hinder our ability to speculatively issue multiple iterations of a loop. If we are able to profile loops during runtime, we can use this information to more accurately issue speculative paths through loop bodies. In this paper we present a characterization of loop execution across the SPECint2000 benchmark suite. We intend for this study to serve as a guide in the selection of design parameters of a loop path predictor We characterize the patterns exhibited during multiple visits to a loop body. We present the design of a table that records path-based loop execution history and allows us to predict multiple loop iterations dynamically.

关键词： Runtime Dynamic range History Computer aided instruction Computer architecture programming profession Iterative algorithms parallel processing Terminology

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Advanced Dataflow programming using Actor Machines for High-Level Synthesis 20

Advanced Dataflow Programming using Actor Machines for High-...

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Proceedings of the 2020 ACM/SIGDA international symposium on Field-Programmable Gate Arrays

作者： Endri Bezati Mahyar Emami James Larus École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781450370998

The use of parallelism has increased drastically in recent years. parallel platforms come in many forms: multi-core processors, embedded hybrid solutions such as multi-processor system-on-chip with reconfigurable logic, and cloud datacenters with multi-core and reconfigurable logic. These heterogeneous platforms can offer massive parallelism, but it can be difficult to exploit, particularly when combining solutions constructed with multiple architectures. To program a heterogeneous platform, a developer must master different programming languages, tools, and APIs to program each aspect of platform separately and then must find a means to connect them with communication interfaces. The motivation of this work is to provide a single programming model and framework for hardware-software stream programs on heterogeneous platforms. Our framework, StreamBlocks, starts with a dataflow programming model for both embedded and datacenter platforms. Dataflow programming is an alternative model of computation that captures both data and task parallelism. We describe a compiler infrastructure for CAL dataflow programs for hardware code generation. CAL is a dataflow programming language that can express multiple dataflow models of computation. StreamBlocks is based on the Tycho compiler infrastructure, which transforms each actor in a dataflow program to an abstract machine model, called Actor Machine. Actor Machines provides a unified model for executing actors in both hardware and software and permit our compiler extension and backend to generate efficient FPGA code. Unlike other systems, the programming model and compiler directly support hardware-software systems in which an FPGA functions as a coprocessor to a CPU. This permits easy integration with existing workflows.

关键词： hls opencl cal dataflow actor machine stream programming fpga

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parallel Approximations of the Tukey g-and-h Likelihoods and Predictions for Non-Gaussian Geostatistics

Parallel Approximations of the Tukey g-and-h Likelihoods and...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Sagnik Mondal Sameh Abdulah Hatem Ltaief Ying Sun Marc G. Genton David E. Keyes Computer Electrical and Mathematical Sciences and Engineering Division King Abdullah University of Science and Technology Thuwal Kingdom of Saudi Arabia Statistics Program King Abdullah University of Science and Technology Extreme Computing Research Center King Abdullah University of Science and Technology

Maximum likelihood estimation is an essential tool in the procedure to impute missing data in climate/weather applications. By defining a particular statistical model, the maximum likelihood estimation can be used to understand the underlying structure of given geospatial data. The Gaussian random field has been widely used to describe geospatial data, as one of the most popular models under the hood of maximum likelihood estimation. Computation of Gaussian log-likelihood demands operations on a dense symmetric positive definite matrix, often parameterized by the Matérn correlation function. This computation of the log-likelihood requires $\mathcal{O}(n^{2})$ storage and $\mathcal{O}(n^{3})$ operations, which can be a huge task considering that the number of geographical locations, $n$ , now commonly reaches into the millions. However, despite its appealing theoretical properties, the assumptions of Gaussianity may be unrealistic since real data often show signs of skewness or have some extreme values. Herein, we consider the Tukey ${g-}$ and $-h$ (TGH) random field as an example of a non-Gaussian random field that shows more robustness in modeling geospatial data by including two more parameters to incorporate skewness and heavy tail features in the model. This work provides the first HPC implementation of the TGH random field's inference on parallel hardware architectures. Using task-based programming models associated with dynamic runtime systems, our implementation leverages the high concurrency of current parallel systems. This permits to run the exact log-likelihood evaluation of the Tukey g-and-h (TGH) random fields for a decent number of geospatial locations. To tackle large-scale problems, we provide additionally an implementation of the given model using two different low-rank approximations. We compress the aforementioned positive-definite symmetric matrix for computing the log-likelihood and rely on the Tile Low-Rank (TLR) and the Hierarchical Off-Diagon

关键词： Maximum likelihood estimation Symmetric matrices Runtime Computational modeling Linear algebra Tail Predictive models

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A Framework for an Automatic Hybrid MPI+OpenMP code generation 11

A Framework for an Automatic Hybrid MPI+OpenMP code generati...

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Simulation Multiconference

作者： Khaled Hamidouche Joel Falcou Daniel Etiemble Laboratoire de Recherche en Informatique University Paris-Sud XI

ISBN: (纸本)9781617828409

Clusters of symmetric multiprocessors (SMPs) are the most currently used architecture for large scale applications and combining MPI and OpenMP models is regarded as a suitable programming model for such architectures. But writing efficient MPI+OpenMP programs requires expertise and performance analysis to determine the best number of processes and threads for the optimal execution for a given application on a given platform. To solve these problems, we propose a framework for the development of hybrid MPI+OpenMP programs. This paper provides the following contributions: (i) A compiler analyser that estimates the computing time of a sequential function. (ii) A code generator tool for generating hybrid code based on the compiler analyser and a simple analytical parallel performance prediction model to estimate the execution time of an hybrid program. (iii) An evaluation of the accuracy of the framework and its usability on several benchmarks.

关键词： Generic programming Bulk Synchronous parallelism Performance Prediction OpenMP MPI MPI+OpenMP performance prediction message passing mannose phosphate isomerase remote procedure calls generic program Code generation Frameworks hybrid coding execution time hybrid computer programming ARCHITECTURE Analysers compilers HYBRID Hybrid electric vehicles

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