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QoS-aware Dynamic Service Caching and Updating in Cost-efficient Multi-Access Edge Computing

QoS-aware Dynamic Service Caching and Updating in Cost-effic...

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international symposium on parallel and Distributed Processing with Applications, ISPA

作者： Shuaibing Lu Xin Jin Jie Wu Shuyang Zhou Shen Wu Jackson Yang Ran Yan College of Computer Science Beijing University of Technology Beijing China Center for Networked Computing Temple University USA School of Software Engineering Beijing Jiaotong University Beijing China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

In the context of mobile edge computing, achieving dynamic service caching and updating to guarantee the QoS of users and reduce system costs is a challenging problem. However, existing research still has certain deficiencies in considering the dynamic behavior of users and the limited storage resources of edge servers. To address this problem, this paper proposes three novel strategies for the different stages of service caching and updating to jointly optimize the delay and cost. At the initial service caching stage, we propose a caching strategy based on dynamic programming, taking into account the constraint of limited memory resources. Given the dynamic behavior of users, we formulate the joint optimization problem as a Markov Decision Process (MDP) and design a service extension strategy based on Q-learning at the service updating decision-making stage and a replacement strategy taking both the distribution of service replications and service access frequency into account at the service updating replacement stage to guarantee the QoS of users. We effectively tackle the challenges arising from the dynamic behavior of users and limited storage resources. Through extensive comparative experiments, our approach outperforms traditional strategies by significantly reducing user latency and system cost.

关键词： Costs Multi-access edge computing Q-learning Heuristic algorithms Memory management Quality of service Dynamic scheduling Dynamic programming Servers Optimization

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A Distributed, Asynchronous Algorithm for Large-Scale Internet Network Topology Analysis

A Distributed, Asynchronous Algorithm for Large-Scale Intern...

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： Youssef Elmougy Akihiro Hayashi Vivek Sarkar Georgia Institute of Technology Atlanta GA USA

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

With the growing complexity of modern internet networks, we introduce a distributed, asynchronous, and scalable algorithm tailored for determining the centrality and importance of various levels of the global internet network topology at a massive scale. By utilizing triangle formations and neighborhood densities in these complex networks, our algorithm provides valuable insights into the structural importance of individual nodes and the intricate relationships among interconnected entities. Focusing on the global internet's prime components — routers, IP addresses, and Autonomous Systems — the algorithm provides a scalable solution extending to the global internet infrastructure, datacenters, cloud networks, and private networks. By taking advantage of the parallelism, distributed processing, efficient communication, and fine-grained asynchronous execution through an Actor-based programming system, our algorithm is capable of efficiently processing and performing rapid computations on large-scale internet networks. We perform scalability studies on the NERSC Perlmutter supercomputer and the Georgia Tech HPC PACE cluster using three large-scale real-world network datasets and one large-scale synthetic network dataset, achieving up to 91.7% parallel efficiency scaling out to 2K cores and reducing execution time from 5.7 hours to 18.3 seconds, while performing 105.4× better on average compared to related approaches. Our research contributes significantly to facilitating enhanced network management, fault tolerance and resilience, and security, but as well to improving overall network stability, reducing latency, and optimizing energy consumption across the vast internet network devices environment.

关键词： Performance evaluation Cloud computing Scalability Clustering algorithms programming parallel processing Supercomputers Stability analysis Security Resilience

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FPGA-based accelerator design from a domain-specific language

FPGA-based accelerator design from a domain-specific languag...

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international Conference on Field Programmable Logic and Applications

作者： M. Akif Özkan Oliver Reiche Frank Hannig Jürgen Teich Friedrich-Alexander University of Erlangen-Ntirnberg (FAU) Germany

A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL's data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.

关键词： Kernel Hardware Computer architecture programming Field programmable gate arrays Image processing

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Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs

Modeling, programming and performance analysis of automotive...

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IEEE international High-Level Design Validation and Test Workshop

作者： Jorg Fickenscher Oliver Reiche Jens Schlumberger Frank Hannig Jurgen Teich Hardware/Software Co-Design University Erlangen-Nürnberg (FAU) Germany

Future Advanced Driver Assistance Systems (ADAS) require the continuous computation of detailed maps of the vehicle's environment. Due to the high demand of accuracy and the enormous amount of data to be fused and processed, common architectures used today, like single-core processors in automotive Electronic Control Units (ECUs), do not provide enough computing power. Here, emerging embedded multi-core architectures are appealing such as embedded Graphics Processing Units (GPUs). In this paper, we (a) identify and analyze common subalgorithms of ADAS algorithms for computing environment maps, such as interval maps, for suitability to be parallelized and run on embedded GPUs. From this analysis, (b) performance models are derived on achievable speedups with respect to sequential single-core CPU implementations. (c) As a third contribution of this paper, these performance models are validated by presenting and comparing a novel parallelized interval map GPU implementation against a parallel occupancy grid map implementation. For both types of environment maps, implementations on an Nvidia Tegra K1 prototype are compared to verify the correctness of the introduced performance models. Finally, the achievable speedups with respect to a single-core CPU solution are reported. These range from 3x to 275x for interval and grid map computations.

关键词： Graphics processing units Sensors Vehicles Computational modeling Algorithm design and analysis Two dimensional displays Automotive engineering

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Bluehive - A field-programable custom computing machine for extreme-scale real-time neural network simulation

Bluehive - A field-programable custom computing machine for ...

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Annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Simon W. Moore Paul J. Fox Steven J.T. Marsh A. Theodore Markettos Alan Mujumdar Computer Laboratory University of Cambridge Cambridge UK

Bluehive is a custom 64-FPGA machine targeted at scientific simulations with demanding communication requirements. Bluehive is designed to be extensible with a reconfigurable communication topology suited to algorithms with demanding high-bandwidth and low-latency communication, something which is unattainable with commodity GPGPUs and CPUs. We demonstrate that a spiking neuron algorithm can be efficiently mapped to Bluehive using Bluespec System Verilog by taking a communication-centric approach. This contrasts with many FPGA-based neural systems which are very focused on parallel computation, resulting in inefficient use of FPGA resources. Our design allows 64k neurons with 64M synapses per FPGA and is scalable to a large number of FPGAs.

关键词： Field programmable gate arrays Neurons Mathematical model Equations Delay Bandwidth programming

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Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC

Towards efficient and concurrent FFTs implementation on Inte...

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international symposium on Circuits and Systems

作者： Mounir Khelifi Daniel Massicotte Yvon Savaria Université du Québec à Trois-Rivières Electrical and Computer Engineering Department Trois-Rivières Québec Canada Laboratoire des Signaux et Systèmes Intégrés Groupe de recherche en électronique industrielle école Polytechnique de Montréal Electrical Engineering Department Montréal Quebec Canada

ISBN: (纸本)9781479953424

Fast Fourier Transform (FFT) is an important part of many applications, such as in wireless communication based on OFDM (Orthogonal Frequency Division Multiplexing). With Cloud Radio Access Networks, implementing FFTs on multiprocessor clusters is a challenging task. For instance, supporting the Long Term Evolution (LTE) protocol requires processing 100 independent FFTs (with sizes ranging from 128 to 2048 points) in 66.7 μs. In this work, seven native FFT candidate implementations are compared. The considered implementation environments are: OpenMP (Open Multi-Processing) on 1 core, MPI (Message Passing Interface) on 1 core, 2 cores, and 3 cores, Hybrid OpenMP+MPI on 1 core and 3 cores, and MPI on an heterogeneous platform composed of Xeon-Phi and 3 cores. The reported experimental results show that the latter method meets the latency requirements of LTE. It is shown that the OpenMP and MPI paradigms running only on MICs (Many Integrated Cores) cannot benefit fully from the computing capability of many-core architectures. The heterogeneous combination of Xeon+MICs provides a better performance.

关键词： Multi-core LTE OFDM FFT parallel programming Many Integrated Core (MIC) MKL OpenMP MPI Hybrid Many-core

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A Dask Distributed Radio Astronomy Reduction Framework

A Dask Distributed Radio Astronomy Reduction Framework

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General Assembly and Scientific symposium, URSI

作者： Simon J. Perkins Hertzog L. Bester Benjamin Hugo Jonathan S. Kenyon Oleg M. Smirnov SARAO Cape Town Western Cape South Africa Rhodes University Makhanda Eastern Cape South Africa

Interferometric coherency measurements scale quadratically with the number of stations in the interferometer. This, combined with high spectro temporal resolution of the data necessitates the use of modern computing strategies such as MapReduce, and cluster computing frameworks to reduce data in tractable amounts of time. Frameworks such as Spark and Dask [1] lean towards a streaming, chunked, functional programming style with minimal shared state. Individual tasks processing chunks of data are flexibly scheduled on multiple cores and nodes. To process the quantities of data produced by contemporary radio telescopes such as MeerKAT, and future telescopes such as the SKA, radio astronomy codes must adapt to these paradigms. In what follows, we describe two Python libraries, dask-ms and codex-africanus, which enable the development of distributed High-Performance Radio Astronomy code.

关键词： Codes Radio astronomy Clustering algorithms Telescopes parallel processing Libraries Sparks

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Speculative dynamic vectorization

Speculative dynamic vectorization

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Annual international symposium on Computer Architecture, ISCA

作者： A. Pajuelo A. Gonzalez M. Valero Departament d'Arquitectura de Computadors Universitat Poliltècnica de Catalunya Barcelona Spain

Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also present in irregular or pointer-rich codes, for which the compiler is quite limited to discover it. In this paper we propose a microarchitecture extension in order to exploit SIMD parallelism in a speculative way. The idea is to predict when certain operations are likely to be vectorizable, based on some previous history information. In this case, these scalar instructions are executed in a vector mode. These vector instructions operate on several elements (vector operands) that are anticipated to be their input operands and produce a number of outputs that are stored on a vector register in order to be used by further instructions. Verification of the correctness of the applied vectorization eventually changes the status of a given vector element from speculative to non-speculative, or alternatively, generates a recovery action in case of misspeculation. The proposed microarchitecture extension applied to a 4-way issue superscalar processor with one wide bus is 19% faster than the,same processor with 4 scalar buses to Ll data cache. This speed up is due basically to 1) the reduction in number of memory accesses, 15% for SpecInt and 20% for SpecFP, 2) the transformation of scalar arithmetic instructions into their vector counterpart, 28% for SpecInt and 23% for SpecFP, and 3) the exploitation of control independence for mispredicted branches.

关键词： parallel processing Streaming media Computer architecture Microarchitecture History Arithmetic Program processors programming profession Instruction sets Concurrent computing

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Comparative Analysis of the Architecture of Dual-Core Blackfin Digital Signal Processors

Comparative Analysis of the Architecture of Dual-Core Blackf...

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international Conference on Information Science and Communications Technologies (ICISCT)

作者： Hakimjon Zaynidinov Sanjarbek Ibragimov Gayrat Tojiboyev Tashkent University of Information Technologies Tashkent Uzbekistan Andijan Machine Building Institute Andijan Uzbekistan Andijan State University Andijan Uzbekistan

ISBN: (纸本)9781665432597

Nowadays, special processors are widely used in digital processing of signals. Analog devices are one of the largest companies producing custom processors. This article compares and analyzes the functional descriptions of Analog Devices' Blackfin dual-core processor architecture. The architectures of the ADSP-BF561 and ADSP-BF60x processors are described, their capabilities and areas of application are described. The peripherals of single-core and dual-core processors are compared in the table. The core architecture of Blackfin processors is given and its constituents are described. The hierarchical memory architecture of dual-core Blackfin processors is given. Also included are tables comparing the internal memory of the Blackfin processor family, first-class L1 memory in the core. The internal memories of ADSP-BF561 and ADSP-BF60x Blackfin processors are compared.

关键词： Information science Program processors parallel programming Memory management Memory architecture Digital signal processors Signal processing algorithms

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Hierarchical parallel algorithms for Module Placement of Large Chips on Distributed Memory architectures

Hierarchical Parallel Algorithms for Module Placement of Lar...

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2002 international symposium on Distributed Computing and Applications for Business Engineering and Science

作者： Laurence Tianruo Yang Department of Computer Science St.Francis Xavier University P.O.Box 5000AntigonishB2G 2W5NSCanada

The PROUD module placement algorithm mainly uses a hierarchical decomposition technique and the solution of sparse linear systems based on a resistive network analogy. It has been shown that the PROUD algorithm can achieve a comparable design of the placement problems for very large circuits with the best placement algorithm based on simulated annealing, but with several order of magnitude faster. The modified PROUD, namely MPROUD algorithm by perturbing the coefficient matrices performs much faster that the original PROUD algorithm. Due to the instability and unguaranteed convergence of MPROUD algorithm, we have proposed a new convergent and numerically stable PROUD, denoted as SPROUD, with attractive computational costs to solve the module placement problems by making use of the SYMMLQ method based on Lanczos process in [16]. In this paper, we subsequently propose a parallel version of the SPROUD algorithm. The parallel algorithm is derived such that all inner products and matrix-vector multiplications of a single iteration step are independent. Therefore, the cost of global communication which represents the bottleneck of the parallel performance on parallel distributed memory computers can be significantly reduced, therefore, to obtain another order of magnitude improvement in the runtime without loss of the quality of the layout.

关键词： Chip module placement, large and sparse linear systems with symmetric indefinite coefficients, parallel systems, the SPROUD algorithm, Lanczos process, the SYMMLQ method

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