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Anton: a special-purpose machine that achieves a hundred-fold speedup in biomolecular simulations 13

Anton: a special-purpose machine that achieves a hundred-fol...

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Proceedings of the 22nd international symposium on High-performance parallel and distributed computing

作者： David E. Shaw D. E. Shaw Research Center for Computational Biology & Bioinformatics Columbia University New York NY USA

ISBN: (纸本)9781450319102

Molecular dynamics (MD) simulation has long been recognized as a potentially transformative tool for understanding the behavior of proteins and other biological macromolecules, and for developing a new generation of precisely targeted drugs. Many biologically important phenomena, however, occur over timescales that have previously fallen far outside the reach of MD technology. We have constructed a specialized, massively parallel machine, called Anton, that is capable of performing atomic-level simulations of proteins at a speed roughly two orders of magnitude beyond that of the previous state of the art. The machine has now simulated the behavior of a number of proteins for periods as long as two milliseconds -- approximately 200 times the length of the longest such simulation previously published -- revealing aspects of protein dynamics that were previously inaccessible to both computational and experimental study. The speed at which Anton performs these simulations is in large part the result of a tightly coupled codesign process in which the machine architecture was developed in concert with novel algorithms, including an asymptotically optimal parallel algorithm (with highly attractive constant factors) for the range-limited N-body problem.

关键词： computational chemistry hardware/software co-design computational biology computer-aided drug design parallel architectures molecular dynamics simulation

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Using Dynamic parallelism for Fine-Grained, Irregular Workloads: A Case Study of the N-Queens Problem

Using Dynamic Parallelism for Fine-Grained, Irregular Worklo...

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international symposium on Computing and Networking (CANDAR)

作者： Max Plauth Frank Feinbube Frank Schlegel Andreas Polze Operating Systems and Middleware Group University of Potsdam Potsdam Germany

GPU compute devices have become very popular for general purpose computations. However, the SIMD-like hardware of graphics processors is currently not well suited for irregular workloads, like searching unbalanced trees. In order to mitigate this drawback, NVIDIA introduced an extension to GPU programming models called dynamic parallelism. This extension enables GPU programs to spawn new units of work directly on the GPU, allowing the refinement of subsequent work items based on intermediate results without any involvement of the main CPU. This work investigates methods for employing dynamic parallelism with the goal of improved workload distribution for tree search algorithms on modern GPU hardware. For the evaluation of the proposed approaches, a case study is conducted on the n-queens problem. Extensive benchmarks indicate that the benefits of improved resource utilization fail to outweigh high management overhead and runtime limitations due to the very fine level of granularity of the investigated problem. However, novel memory management concepts for passing parameters to child grids are presented. These general concepts are applicable to other, more coarse-grained problems that benefit from the use of dynamic parallelism.

关键词： Graphics processing units parallel processing Instruction sets Kernel Memory management Message systems Hardware

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Modular verification of collaboration-based software designs 9

Modular verification of collaboration-based software designs

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Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering

作者： Kathi Fisler Shriram Krishnamurthi Department of Computer Science Worcester Polytechnic Institute Worcester MA Computer Science Department Brown University Providence RI

ISBN: (纸本)9781581133905

Most existing modular model checking techniques betray their hardware roots: they assume that modules compose in parallel. In contrast, collaboration-based software designs, which have proven very successful in several domains, are sequential in the simplest case. Most interesting collaboration-based designs are really quasi-sequential compositions of parallel compositions. These designs demand and inspire new verification techniques. This paper presents algorithms that exploit the software's modular decomposition to verify collaboration-based designs. Our technique can verify most properties locally in the collaborations; we also characterize when a global state space construction is unavoidable. We have validated our proposal by testing it on several designs.

关键词： model checking collaboration-based design aspect-oriented programming computer-aided verification compositional reasoning software architecture

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Optimal Triangulation on the High Bandwidth Memory Model

Optimal Triangulation on the High Bandwidth Memory Model

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Koji Nakano Victor Poupet Graduate School of Advanced Science and Engineering Hiroshima University Higashi Hiroshima Japan LIRMM University of Montpellier CNRS Montpellier France

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The High Bandwidth Memory (HBM) model is a theoretical computing model consisting of a logic circuit with a large external memory. Each address of the external memory can store $p$ elements which can be read or written at the same time. Access to $p$ elements stored at a given address in the external memory has a latency of $l$ clock cycles. However, access to any $k$ consecutive addresses can be done only in $(k+l-1)$ clock cycles in a pipeline fashion by burst mode. A hardware algorithm is implemented in a logic circuit of the HBM to solve a particular problem. In this paper, we present an optimal implementation of the $O(n^{3})$ -time dynamic programming algorithm for solving the optimal polygon triangulation (OPT) problem which is a problem to find a triangulation with minimum total weight of an input convex n-gon with weighted cords. We assume that the input weight matrix of a convex n-gon is stored in the external memory of the HBM model. Our hardware algorithm implemented in the logic circuit of size $O(s^{2})$ operates on it and computes the optimal polygon triangulation of the input polygon in $O(\frac{n^{3}}{sp}+\frac{n^{3}}{s^{2}}+\frac{n^{3}}{s^{3}}l)$ time. We also provide a theoretical proof showing that any hardware algorithm in a logic circuit of size $O(s^{2})$ takes at least $\Omega(\frac{n^{3}}{sp}+\frac{n^{3}}{s^{2}})$ time to solve the OPT problem. Thus, our implementation is optimal whenever $s^{2}\geq lp$ or $s\geq l$ , and this optimality condition is always satisfied from a practical point of view.

关键词： Heuristic algorithms Logic circuits Computational modeling Optimized production technology Bandwidth programming Hardware

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Software Transactional Memory for GPU architectures 14

Software Transactional Memory for GPU Architectures

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Proceedings of Annual IEEE/ACM international symposium on Code Generation and Optimization

作者： Yunlong Xu Rui Wang Nilanjan Goswami Tao Li Lan Gao Depei Qian School of Electronic and Information Engineering Xi'an Jiaotong University Xi'an China School of Computer Science and Engineering Beihang University Beijing China ECE Department University of Florida Gainesville USA School of Electronic and Information Engineering Xi'an Jiaotong University Xi'an China and School of Computer Science and Engineering Beihang University Beijing China

ISBN: (纸本)9781450326704

Modern GPUs have shown promising results in accelerating computation intensive and numerical workloads with limited dynamic data sharing. However, many real-world applications manifest ample amount of data sharing among concurrently executing threads. Often data sharing requires mutual exclusion mechanism to ensure data integrity in multithreaded environment. Although modern GPUs provide atomic primitives that can be leveraged to construct fine-grained locks, lock-based synchronization requires significant programming efforts to achieve functional correctness. The massive multithreading and SIMT execution paradigm of GPUs further extend the challenges of GPU *** make applications with dynamic data sharing benefit from GPU acceleration, we propose a novel software transactional memory system for GPU architectures (GPU-STM). The major challenges include ensuring good scalability with respect to the massive multithreading of GPUs, and preventing livelocks caused by the SIMT execution paradigm of GPUs. To this end, we propose (1) a hierarchical validation technique and (2) an encounter-time lock-sorting mechanism to deal with the two challenges, respectively. We build our GPU-STM prototype based on the commercially available GPU platform and runtime. Our real system based evaluation shows that GPU-STM outperforms coarse-grain locks on GPUs by up to 20x.

关键词： Software Transactional Memory parallel programming General-Purpose GPU Computing

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An efficient handwritten digit recognition method on a flexible parallel architecture

An efficient handwritten digit recognition method on a flexi...

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international Conference on Microelectronics for Neural Networks

作者： A.P. Maubant Y. Autret G. Leonhard G. Ouvradou A. Thepaut Télécom Bretagne Arte Laboratory Brest France

This paper presents neural and hybrid (symbolic and subsymbolic) applications downloaded on the distributed computer architecture ArMenX. This machine is articulated around a ring of FPGAs acting as routing resources as well as fine grain computing resources and thus giving great flexibility. More coarse grain computing resources-Transputer and DSP-tightly coupled via FPGAs give a large application spectrum to the machine, making it possible to implement heterogeneous algorithms efficiently involving both low level (computing intensive) and high level (control intensive) tasks. We first introduce the ArMenX project and the main architecture features. Then, after giving details on the computing of propagation and back-propagation of the multi-layer perceptron on ArMenX, we will focus on a handwritten digit (issued from a zip code data base) recognition application. An original and efficient method, involving three neural networks, is developed. The first two neural networks deal with the 'reading process', and the last neural network, which learned to write, helps to make decisions on the first two network outputs, when they are not confident. Before concluding, the paper presents the work of integration of ArMenX into a high level programming environment, designed to make it easier to take advantage of the architecture flexibility.

关键词： Handwriting recognition parallel architectures Field programmable gate arrays Neural networks Computer architecture Digital signal processing Application software Multilayer perceptrons Laboratories Routing

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MediaBench: a tool for evaluating and synthesizing multimedia and communications systems 30

MediaBench: a tool for evaluating and synthesizing multimedi...

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IEEE/ACM international symposium on Microarchitecture (MICRO)

作者： Chunho Lee M. Potkonjak W.H. Mangione-Smith The Departments of Computer Science University of California Los Angeles USA The Departments of Computer Science and Electrical Engineering University of California Los Angeles USA

ISBN: (纸本)9780818679773

Significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of general-purpose computing, and more specifically the SPEC benchmark suite. At the same time, a number of microprocessor architectures have emerged which have VLIW and SIMD structures that are well matched to the needs of the ILP compilers. Most of these processors are targeted at embedded applications such as multimedia and communications, rather than general-purpose systems. Conventional wisdom, and a history of hand optimization of inner-loops, suggests that ILP compilation techniques are well suited to these applications. Unfortunately, there currently exists a gap between the compiler community and embedded applications developers. This paper presents MediaBench, a benchmark suite that has been designed to fill this gap. This suite has been constructed through a three-step process: intuition and market driven initial selection, experimental measurement to establish uniqueness, and integration with system synthesis algorithms to establish usefulness.

关键词： Multimedia communication Multimedia systems Computer architecture Application software parallel processing Microprocessors VLIW Program processors Pipeline processing Digital signal processing

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parallel Approximations for High-Dimensional Multivariate Normal Probability Computation in Confidence Region Detection Applications

Parallel Approximations for High-Dimensional Multivariate No...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Xiran Zhang Sameh Abdulah Jian Cao Hatem Ltaief Ying Sun Marc G. Genton David E. Keyes Computer Electrical and Mathematical Sciences and Engineering Division King Abdullah University of Science and Technology Statistics Program King Abdullah University of Science and Technology Extreme Computing Research Center King Abdullah University of Science and Technology Thuwal Saudi Arabia Department of Mathematics The University of Houston Houston Texas USA

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Addressing the statistical challenge of computing the multivariate normal (MVN) probability in high dimensions holds significant potential for enhancing various applications. For example, the critical task of detecting confidence regions where a process probability surpasses a specific threshold is essential in diverse applications, such as pinpointing tumor locations in magnetic resonance imaging (MRI) scan images, determining hydraulic parameters in groundwater flow issues, and forecasting regional wind power to optimize wind turbine placement, among numerous others. One common way to compute high-dimensional MVN probabilities is the Separation-of-Variables (SOV) algorithm. This algorithm is known for its high computational complexity of O(n 3 ) and space complexity of O(n 2 ), mainly due to a Cholesky factorization operation for an n×n covariance matrix, where n represents the dimensionality of the MVN problem. This work proposes a high-performance computing framework that allows scaling the SOV algorithm and, subsequently, the confidence region detection algorithm. The framework leverages parallel linear algebra algorithms with a task-based programming model to achieve performance scalability in computing process probabilities, especially on large-scale systems. In addition, we enhance our implementation by incorporating Tile Low-Rank (TLR) approximation techniques to reduce algorithmic complexity without compromising the necessary accuracy. To evaluate the performance and accuracy of our framework, we conduct assessments using simulated data and a wind speed dataset. Our proposed implementation effectively handles high-dimensional multivariate normal (MVN) probability computations on shared and distributed-memory systems using finite precision arithmetics and TLR approximation computation. Performance results show a significant speedup of up to 20X in solving the MVN problem using TLR approximation compared to the reference dense solution without sacrificin

关键词： Accuracy Tensors Wind speed Magnetic resonance imaging Linear algebra Wind power generation Approximation algorithms

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VLSI implementations of the cryptographic hash functions MD6 and ïrRUPT

VLSI implementations of the cryptographic hash functions MD6...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： L. Henzen F. Carbognani J.-Ph. Aumassony S. O'Neil Wolfgang Fichtner IIS ETH Zurich Switzerland IIS ETH Zurich Switzerland FHNW Windisch Switzerland VEST Corporation France

ISBN: (纸本)9781424438273

A public competition organized by the NIST recently started, with the aim of identifying a new standard for cryptographic hashing (SHA-3). Besides a high security level, candidate algorithms should show good performance on various platforms. While an average performance on high-end processors is generally not critical, implementability and flexibility in hardware is crucial, because the new standard will be implemented in a variety of lightweight devices. This paper investigates VLSI architectures of the SHA-3 candidates MD6 and irRUPT. The fastest circuit is the 16timesparallel MD6 core, reaching 16.3 Gbps at a complexity of 69.8 k gate equivalents (GE) on ASIC and 8.4 Gbps using 4465 Slices on FPGA. However, large memory requirements preclude the application of MD6 to resource-constrained systems. The most flexible and efficient circuit turns out to be our 2-irRUPT64times2-256/8 core, which achieves a throughput of 5.0 Gbps at 12.7 kGE on ASIC and 1.7 Gbps using 613 Slices on FPGA.

关键词： Very large scale integration Cryptography Hardware NIST Application specific integrated circuits Field programmable gate arrays National security Flexible printed circuits Throughput parallel processing

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Managing Power Demand and Load Imbalance to Save Energy on Systems with Heterogeneous CPU Speeds

Managing Power Demand and Load Imbalance to Save Energy on S...

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international symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Edson Luiz Padoin Matthias Diener Philippe O. A. Navaux Jean-François Méhaut Department of Exact Sciences and Engineering (DCEEng) Regional University of Northwest of Rio Grande do Sul (UNIJUI) Ijuí Brazil Parallel Programming Laboratory (PPL) University of Illinois at Urbana-Champaign (UIUC) Urbana-Champaign USA Informatics Institute Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil University Grenoble Alpes Grenoble France

Different simulations of real problems have been executed in High Performance Computing systems. However, the power consumption of these systems is an increasing concern once more energy are consumed to large simulations. In this context, load balancers emerge as a promising alternative for supporting the computational science methods. In response to this challenge, we developed a new heterogeneous energy-aware load balancer called H-ENERGYLB to reduce the average power demand of systems with heterogeneous processors and save energy when scientific applications with imbalanced load are executed. Our new load balancing strategy combines dynamic load balancing with DVFS techniques to mitigate the imbalanced workloads in order to reduce the clock frequency of underloaded computing cores which experience some residual imbalance even after tasks are remapped. Experiments with three applications on two different heterogeneous architectures show that H-ENERGYLB results in power reductions of 7.14% in average with the energy saving of 36.6% in average compared to others load balancers.

关键词： Program processors Load management Task analysis Power demand Clocks Runtime Load modeling

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