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Compiler optimization-space exploration

Compiler optimization-space exploration

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international symposium on Code Generation and Optimization (CGO)

作者： S. Triantafyllis M. Vachharajani N. Vachharajani D.I. August Departments of Computer Science and Electrical Engineering Princeton University Princeton NJ USA

To meet the demands of modern architectures, optimizing compilers must incorporate an ever larger number of increasingly complex transformation algorithms. Since code transformations may often degrade performance or interfere with subsequent transformations, compilers employ predictive heuristics to guide optimizations by predicting their effects a priori. Unfortunately, the unpredictability of optimization interaction and the irregularity of today's wide-issue machines severely limit the accuracy of these heuristics. As a result, compiler writers may temper high variance optimizations with overly conservative heuristics or may exclude these optimizations entirely. While this process results in a compiler capable of generating good average code quality across the target benchmark set, it is at the cost of missed optimization opportunities in individual code segments. To replace predictive heuristics, researchers have proposed compilers which explore many optimization options, selecting the best one a posteriori. Unfortunately, these existing iterative compilation techniques are not practical for reasons of compile time and applicability. We present the Optimization-Space Exploration (OSE) compiler organization, the first practical iterative compilation strategy applicable to optimizations in general-purpose compilers. Instead of replacing predictive heuristics, OSE uses the compiler writer's knowledge encoded in the heuristics to select a small number of promising optimization alternatives for a given code segment. Compile time is limited by evaluating only these alternatives for hot code segments using a general compile-time performance estimator An OSE-enhanced version of Intel's highly-tuned, aggressively optimizing production compiler for IA-64 yields a significant performance improvement, more than 20% in some cases, on Itanium for SPEC codes.

关键词： Optimizing compilers Computer architecture Resource management Microarchitecture Computer science Degradation Cost function Production parallel processing Performance gain

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Executing dynamic data-graph computations deterministically using chromatic scheduling 14

Executing dynamic data-graph computations deterministically ...

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Proceedings of the 26th ACM symposium on parallelism in algorithms and architectures

作者： Tim Kaler William Hasenplaugh Tao B. Schardl Charles E. Leiserson MIT CSAIL Cambridge MA USA

ISBN: (纸本)9781450328210

A data-graph computation — popularized by such programming systems as Galois, Pregel, GraphLab, PowerGraph, and GraphChi — is an algorithm that performs local updates on the vertices of a graph. During each round of a data-graph computation, an update function atomically modifies the data associated with a vertex as a function of the vertex's prior data and that of adjacent vertices. A dynamic data-graph computation updates only an active subset of the vertices during a round, and those updates determine the set of active vertices for the next *** paper introduces PRISM, a chromatic-scheduling algorithm for executing dynamic data-graph computations. PRISM uses a vertex-coloring of the graph to coordinate updates performed in a round, precluding the need for mutual-exclusion locks or other nondeterministic data synchronization. A multibag data structure is used by PRISM to maintain a dynamic set of active vertices as an unordered set partitioned by color. We analyze PRISM using work-span analysis. Let G=(V,E) be a degree-Δ graph colored with Χ colors, and suppose that Q⊆V is the set of active vertices in a round. Define size(Q)=[Q] + Σv∈Qdeg(v), which is proportional to the space required to store the vertices of Q using a sparse-graph layout. We show that a P-processor execution of PRISM performs updates in Q using O(Χ(lg (Q/Χ)+lgΔ)+ lgP) span and Θ(size(Q)+Χ+P) work. These theoretical guarantees are matched by good empirical performance. We modified GraphLab to incorporate PRISM and studied seven application benchmarks on a 12-core multicore machine. PRISM executes the benchmarks 1.2–2.1 times faster than GraphLab's nondeterministic lock-based scheduler while providing deterministic *** paper also presents PRISM-R, a variation of PRISM that executes dynamic data-graph computations deterministically even when updates modify global variables with associative operations. PRISM-R satisfies the same theoretical bounds as PRISM, but its implementation is

关键词： determinism reducers multithreading parallel programming work stealing data-graph computations chromatic scheduling multicore

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HeAT – a Distributed and GPU-accelerated Tensor Framework for Data Analytics

HeAT – a Distributed and GPU-accelerated Tensor Framework f...

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IEEE international Conference on Big Data

作者： Markus Götz Charlotte Debus Daniel Coquelin Kai Krajsek Claudia Comito Philipp Knechtges Björn Hagemeier Michael Tarnawa Simon Hanselmann Martin Siggel Achim Basermann Achim Streit Steinbuch Centre for Computing (SCC) Karlsruhe Institute of Technology (KIT) Karlsruhe Germany Institute for Software Technology (SC) German Aerospace Center (DLR) Cologne Germany Institute of Bio- and Geosciences Agrosphere (IBG-3) Forschungszentrum Jülich (FZJ) Jülich Germany Jülich Supercomputing Centre (JSC) Forschungszentrum Jülich (FZJ) Jülich Germany

ISBN: (数字)9781728162515

ISBN: (纸本)9781728162522

To cope with the rapid growth in available data, the efficiency of data analysis and machine learning libraries has recently received increased attention. Although great advancements have been made in traditional array-based computations, most are limited by the resources available on a single computation node. Consequently, novel approaches must be made to exploit distributed resources, e.g. distributed memory architectures. To this end, we introduce HeAT, an array-based numerical programming framework for large-scale parallel processing with an easy-to-use NumPy-like API. HeAT utilizes PyTorch as a node-local eager execution engine and distributes the workload on arbitrarily large high-performance computing systems via MPI. It provides both low-level array computations, as well as assorted higher-level algorithms. With HeAT, it is possible for a NumPy user to take full advantage of their available resources, significantly lowering the barrier to distributed data analysis. When compared to similar frameworks, HeAT achieves speedups of up to two orders of magnitude.

关键词： Heating systems Industries Data analysis Big Data parallel processing Libraries Arrays

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Accelerating decoupled look-ahead via weak dependence removal: A metaheuristic approach

Accelerating decoupled look-ahead via weak dependence remova...

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IEEE symposium on High-Performance Computer Architecture

作者： Raj Parihar Michael C. Huang Dept. of Electrical & Computer Engineering University of Rochester Rochester NY USA

Despite the proliferation of multi-core and multi-threaded architectures, exploiting implicit parallelism for a single semantic thread is still a crucial component in achieving high performance. Look-ahead is a tried-and-true strategy in uncovering implicit parallelism, but a conventional, monolithic out-of-order core quickly becomes resource-inefficient when looking beyond a small distance. A more decoupled approach with an independent, dedicated look-ahead thread on a separate thread context can be a more flexible and effective implementation, especially in a multi-core environment. While capable of generating significant performance gains, the look-ahead agent often becomes the new speed limit. Fortunately, the look-ahead thread has no hard correctness constraints and presents new opportunities for optimizations. One such opportunity is to exploit “weak” dependences. Intuitively, not all dependences are equal. Some links in a dependence chain are weak enough that removing them in the look-ahead thread does not materially affect the quality of look-ahead but improves the speed. While there are some common patterns of weak dependences, they can not be generalized as heuristics in generating better code for the look-ahead thread. A primary reason is that removing a false weak dependence can be exceedingly costly. Nevertheless, a trial-and-error approach can reliably identify opportunities for improving the look-ahead thread and quantify the benefits. A framework based on genetic algorithm can help search for the right set of changes to the look-ahead thread. In the set of applications where the speed of look-ahead has become the new limit, this method is found to improve the overall system performance by up to 1.48x with a geometric mean of 1.14x over the baseline decoupled look-ahead system, while reducing energy consumption by 11%.

关键词： Genetic algorithms Skeleton parallel processing Message systems Instruction sets Registers Context

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Scheduling with Fully Compressible Tasks: Application to Deep Learning Inference with Neural Network Compression

Scheduling with Fully Compressible Tasks: Application to Dee...

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： Tiago Da Silva Barros Frédéric Giroire Ramon Aparicio-Pardo Stéphane Pérennes Emanuele Natale Université Côte d’Azur/CNRS/I3S/Inria France

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

With the advent and the growing usage of Machine Learning as a Service (MLaaS), cloud and network systems are now offering the possibility to deploy ML tasks on heterogeneous clusters. Then, network and cloud operators have to schedule these tasks, determining both when and on which devices to execute them. In parallel, several solutions, such as neural network compression, were proposed to build small models which can run on limited hardware. These solutions allow choosing the model size at inference time for any targeted processing time without having to re-train the *** this work, we consider the Deadline Scheduling with Compressible Tasks (DSCT) problem: a novel scheduling problem with task deadlines where the tasks can be compressed. Each task can be executed with a certain compression, presenting a trade-off between its compression level (and, its processing time) and its obtained utility. The objective is to maximize the tasks utilities. We propose an approximation algorithm with proved guarantees to solve the problem. We validate its efficiency with extensive simulation, obtaining near optimal results. As application scenario, we study the problem when the tasks are Deep Learning classification jobs, and the objective is to maximize their global accuracy, but we believe that this new framework and solutions apply to a wide range of application cases.

关键词： Deep learning Cloud computing Schedules Processor scheduling Neural network compression programming Scheduling Inference algorithms Hardware Network systems

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The natural work-stealing algorithm is stable

The natural work-stealing algorithm is stable

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IEEE international Conference on Cluster Computing

作者： P. Berenbrink T. Friedetzky L.A. Goldberg Department of Computer Science University of Warwick Coventry UK

In this paper we analyse a very simple dynamic work-stealing algorithm. In the work-generation model, there are n generators which are arbitrarily distributed among a set of n processors. During each time-step, with probability /spl lambda/, each generator generates a unit-time task which it inserts into the queue of its host processor. After the new tasks are generated, each processor removes one task from its queue and services it. Clearly, the work-generation model allows the load to grow more and more imbalanced, so, even when /spl lambda/<1, the system load can be unbounded. The natural work-stealing algorithm that we analyse works as follows. During each time step, each empty processor sends a request to a randomly selected other processor. Any non-empty processor having received at least one such request in turn decides (again randomly) in favour of one of the requests. The number of tasks which are transferred from the non-empty processor to the empty one is determined by the so-called work-stealing function f. We analyse the long-term behaviour of the system as a function of /spl lambda/ and f. We show that the system is stable for any constant generation rate /spl lambda/<1 and for a wide class of functions f. We give a quantitative description of the functions f which lead to stable systems. Furthermore, we give upper bounds on the average system load (as a function of f and n).

关键词： Algorithm design and analysis Load management Computer science Heuristic algorithms Load modeling Upper bound Distributed computing Contracts parallel programming Kernel

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TensorFHE: Achieving Practical Computation on Encrypted Data Using GPGPU

TensorFHE: Achieving Practical Computation on Encrypted Data...

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IEEE symposium on High-Performance Computer Architecture

作者： Shengyu Fan Zhiwei Wang Weizhi Xu Rui Hou Dan Meng Mingzhe Zhang State Key Laboratory of Information Security Institute of Information Engineering CAS Beijing China School of Information Science and Engineering Shandong Normal University Jinan China School of Cyber Security University of Chinese Academy of Sciences Beijing China

In the cloud computing era, privacy protection is becoming pervasive in a broad range of applications (e.g., machine learning, data mining, etc). Fully Homomorphic Encryption (FHE) is considered the perfect solution as it enables privacy-preserved computation on untrusted servers. Unfortunately, the prohibitive performance overhead blocks the wide adoption of FHE (about 10, 000× slower than the normal computation). As heterogeneous architectures have gained remarkable success in several fields, achieving high performance for FHE with specifically designed accelerators seems to be a natural choice. Until now, most FHE accelerators have focused on efficiently implementing one FHE operation at a time based on ASIC and with significantly higher performance than GPU and FPGA. However, recent state-of-the-art FHE accelerators rely on an expensive and large on-chip storage and a high-end manufacturing process (i.e., 7nm), which increase the cost of FHE *** this paper, we propose TensorFHE, an FHE acceleration solution based on GPGPU for real applications on encrypted data. TensorFHE utilizes Tensor Core Units (TCUs) to boost the computation of Number Theoretic Transform (NTT), which is the part of FHE with highest time-cost. Moreover, TensorFHE focuses on performing as many FHE operations as possible in a certain time period rather than reducing the latency of one operation. Based on such an idea, TensorFHE introduces operation-level batching to fully utilize the data parallelism in GPGPU. We experimentally prove that it is possible to achieve comparable performance with GPGPU as with state-of-the-art ASIC accelerators. TensorFHE performs 913 KOPS and 88 KOPS for NTT and HMULT (key FHE kernels) within NVIDIA A100 GPGPU, which is 2.61× faster than state-of-the-art FHE implementation on GPGPU; Moreover, TensorFHE provides comparable performance to the ASIC FHE accelerators, which makes it even 2.9× faster than the F1+ with a specific workload. Such a pure software ac

关键词： Cloud computing Software algorithms Graphics processing units Computer architecture parallel processing Software Servers

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Bridging Architecture and programming for Throughput-Oriented Vision Processing (Abstract Only) 15

Bridging Architecture and Programming for Throughput-Oriente...

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Proceedings of the 2015 ACM/SIGDA international symposium on Field-Programmable Gate Arrays

作者： Amir Momeni Hamed Tabkhi Gunar Schirner David Kaeli Northeastern University Boston MA USA

ISBN: (纸本)9781450333153

With the expansion of OpenCL support across many heterogeneous devices (including FPGAs, GPUs and CPUs), the programmability of these systems has been significantly increased. At the same time, new questions arise about which device should be targeted for each OpenCL software kernel. Once we select a device, then we are left to customize the application, selecting the right granularity of parallelism and frequency of host-to-device communication. In this paper, we study the impact of source-level decisions on the overall execution time when developing OpenCL program across different heterogeneous devices. We focus on two mainstream architecture classes (GPUs and FPGAs), and consider throughput-oriented advanced vision processing. To guide this exploration, we propose a new vertical classification for selecting the grain of parallelism for advanced vision processing applications. To carry out this study we have selected the Mean-shift object tracking algorithm as a representative candidate of advanced vision algorithms. Overall, our evaluation demonstrates that fine-grained parallelism can greatly benefit FPGA execution (up to a 4X speed-up), while a combination of coarse-grained and fine-grained parallelism achieves the best performance on a GPU (up to a 6X speed-up). Also, there can be a large benefit if we can execute both the parallel and serial parts of the program on a FPGA (up to a 21X speed-up).

关键词： parallelism granularity opencl object tracking fpga gpu

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HyGCN: A GCN Accelerator with Hybrid Architecture

HyGCN: A GCN Accelerator with Hybrid Architecture

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IEEE symposium on High-Performance Computer Architecture

作者： Mingyu Yan Lei Deng Xing Hu Ling Liang Yujing Feng Xiaochun Ye Zhimin Zhang Dongrui Fan Yuan Xie State Key Laboratory of Computer Architecture Chinese Academy of Sciences School of Computer Science and Technology University of Chinese Academy of Sciences University of California Santa Barbara Chinese Academy of Sciences

ISBN: (数字)9781728161495

ISBN: (纸本)9781728161501

Inspired by the great success of neural networks, graph convolutional neural networks (GCNs) are proposed to analyze graph data. GCNs mainly include two phases with distinct execution patterns. The Aggregation phase, behaves as graph processing, showing a dynamic and irregular execution pattern. The Combination phase, acts more like the neural networks, presenting a static and regular execution pattern. The hybrid execution patterns of GCNs require a design that alleviates irregularity and exploits regularity. Moreover, to achieve higher performance and energy efficiency, the design needs to leverage the high intra-vertex parallelism in Aggregation phase, the highly reusable inter-vertex data in Combination phase, and the opportunity to fuse phase-by-phase execution introduced by the new features of GCNs. However, existing architectures fail to address these demands. In this work, we first characterize the hybrid execution patterns of GCNs on Intel Xeon CPU. Guided by the characterization, we design a GCN accelerator, HyGCN, using a hybrid architecture to efficiently perform GCNs. Specifically, first, we build a new programming model to exploit the fine-grained parallelism for our hardware design. Second, we propose a hardware design with two efficient processing engines to alleviate the irregularity of Aggregation phase and leverage the regularity of Combination phase. Besides, these engines can exploit various parallelism and reuse highly reusable data efficiently. Third, we optimize the overall system via inter-engine pipeline for inter-phase fusion and priority-based off-chip memory access coordination to improve off-chip bandwidth utilization. Compared to the state-of-the-art software framework running on Intel Xeon CPU and NVIDIA V100 GPU, our work achieves on average 1509× speedup with 2500× energy reduction and average 6.5× speedup with 10× energy reduction, respectively.

关键词： Computer architecture Neural networks Engines parallel processing Aggregates Fuses Hardware

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Real-time Forest Simulation for a Flight Simulator using a GPU: Graphics Card Acceleration

Real-time Forest Simulation for a Flight Simulator using a G...

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3rd international Conference on Information and Communication Technologies, vol.2

作者： Jean-Marc Laferte Guillaume Daussin Jihed Flifla Pascal Haigron Computer Science Department Louis de Brogliete graduate Engineering school Bruz France INSERM U642 Rennes France

This paper concerns the real-time simulation of forests for a flight simulator, exploiting the capacities of recent graphics cards. As we will show, these architectures coupled with recent ergonomic environments like CUDA allow Gprogrammers to implement highly parallelizable algorithms to be executed on GPU, without being specialized in parallel programming. The first results exhibited are quite encouraging and promote these technologies. The algorithm devised can display forests with different tree densities, with performances near real-time, for scenes with about one million trees.

关键词： Computer graphics Image generation Flight simulator Trees rendering Real-time programming GPU (Graphics Processing Unit) CUDA Open GL

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