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ExSAIS: Workshop on Extreme Scaling of AI for Science Message from the workshop chairs

ExSAIS: Workshop on Extreme Scaling of AI for Science Messag...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Svitlana Volkova Robert Rallo

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

ExSAIS: Workshop on Extreme Scaling of AI for Science, brings together researchers in Artificial Intelligence (AI) and High Performance computing (HPC) to enable scientific discovery at scale. The evolution of machine perception to machine learning and reasoning, and ultimately machine intelligence, has a potential to significantly impact acceleration and advancement of autonomous scientific discovery and the operation of scientific instruments. While machine reasoning will enable intelligent systems to better understand and interact with their physical world, machine intelligence through modeling, simulation and automation, closes the gap between experiments, extreme computing, and scientific discovery. In order to usher in this new era of autonomous science, advances in several areas of artificial intelligence and other disciplines e.g., high-performance computing, data engineering need to come together.

关键词： Conferences Artificial intelligence distributed processing Computational modeling Machine intelligence Instruments High performance computing

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Accelerating Sorting on GPUs: A Scalable CUDA Quicksort Revision

Accelerating Sorting on GPUs: A Scalable CUDA Quicksort Revi...

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international symposium on INFOTEH-JAHORINA (INFOTEH)

作者： Mehmed Mujić Irvin Ćatić Samra Behić Amila Hadžibajramović Novica Nosović Tarik Hrnjić Department of Computing and Informatics Faculty of Electrical Engineering University of Sarajevo Sarajevo Bosnia and Herzegovina

In this article, an upgraded version of CUDA-Quicksort - an iterative implementation of the quicksort algorithm suitable for highly parallel multicore graphics processors, is described and evaluated. Three key changes which lead to improved performance are proposed. The main goal was to provide an implementation with increased scalability with the size of data sets and number of cores with modern GPU architectures, which was successfully achieved. The proposed changes also lead to significant reduction in execution time. The execution times were measured on an NVIDIA graphics card, taking into account the possible distributions of the input data.

关键词： Java Multicore processing Scalability Graphics processing units distributed databases Performance gain Virtual machining

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Combined Application of Approximate computing Techniques in DNN Hardware Accelerators

Combined Application of Approximate Computing Techniques in ...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Enrico Russo Maurizio Palesi Davide Patti Habiba Lahdhiri Salvatore Monteleone Giuseppe Ascia Vincenzo Catania University of Catania Italy ESIEE Paris France Niccol&#x00F3 Cusano University Italy

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

This paper applies Approximate computing (AC) techniques to the main elements which form a DNN hardware accelerator, namely, computation, communication, and memory subsystems. Specifically, approximate multipliers for computation, link voltage swing reduction for communication, voltage over-scaling for the internal SRAM memory, and lossy compression of the external DRAM memory are considered. The different AC techniques are applied in isolation as well as in conjunction with each other. A set of representative CNN models are mapped onto the approximated hardware accelerators and the trade-offs performance vs. energy vs. accuracy are derived for the execution of CNN inferences.

关键词： distributed processing Conferences Computational modeling Approximate computing Random access memory Voltage Hardware acceleration

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Teaching Heterogeneous computing Using DPC++

Teaching Heterogeneous Computing Using DPC++

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Joel Fuentes Daniel Ló pez Sebastiá n Gonzá lez Department of Computer Science and Information Technologies Universidad del B&#x00ED o-B&#x00ED o Chill&#x00E1 n Chile

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The evolution of modern computer systems with conventional processors to complex hardware units with heterogeneous accelerators is a reality. In the last decade, the awareness of teaching parallel computing in undergraduate programs has increased, however, the focus has been mainly on multi-core CPUs. GPUs, FPGAs, and other accelerators are now present in most of the devices people use daily, but their programming is still left to experienced engineers. New high-level programming languages for heterogeneous architectures such as DPC++ represent a good opportunity to bring closer inexperienced programmers to accelerators. In this paper, we present a new Heterogeneous computing course with a syllabus focused on the foundations of heterogeneous architectures (multi-core CPUs, GPUs, and FPGAs) and their programming with DPC++. We present results from the experience of teaching this course to undergraduate students. Student evaluation and assessment data show that students engaged with the course's learning activities and there is high satisfaction with the contents covered

关键词： distributed processing Education Graphics processing units Computer architecture parallel processing Heterogeneous networks Hardware

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Challenges and Opportunities in Designing High-Performance and Scalable Middleware for HPC and AI: Past, Present, and Future

Challenges and Opportunities in Designing High-Performance a...

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international symposium on parallel and distributed Processing (IPDPS)

作者： D K Panda

This talk focuses on challenges and opportunities emerging over the years (past, present, and future) in designing middleware for HPC and AI (Deep/Machine Learning) workloads on modern high-end computing systems. The talk initially presents the challenges in designing HPC runtime environments with MPI+X programming models by considering support for dense multi-core CPUs, high-performance interconnects, GPUs, and emerging DPUs. Advanced designs and solutions (such as RDMA, in-network computing, GPUDirect RDMA, on-the-fly compression) to exploit novel features of these emerging technologies and their benefits in the context of MVAPICH2 libraries are presented. Next, the talk focuses on MPI-driven solutions for the Deep/Machine Learning domains to extract performance and scalability for popular Deep Learning frameworks, large out-of-core models, GPUs, and DPUs. MPI-driven solutions to accelerate data science applications like Dask are highlighted. Challenges and experiences in deploying this middleware to the HPC cloud environments for Azure, AWS, and Oracle Cloud are presented. The talk concludes with an overview of the newly established NSF-AI Institute ICICLE (https://***/) to address challenges in designing future high-performance edge-to-HPC/ cloud middleware for AI-driven data-intensive applications.

关键词： Middleware Libraries distributed processing Deep learning Computational modeling Scalability Runtime environment

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A Fine-grained Prefetching Scheme for DGEMM Kernels on GPU with Auto-tuning Compatibility

A Fine-grained Prefetching Scheme for DGEMM Kernels on GPU w...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Jialin Li Huang Ye Shaobo Tian Xinyuan Li Jian Zhang Computer Network Information Center Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Alibaba Group Beijing China

General Matrix Multiplication (GEMM) is one of the fundamental kernels for scientific and high-performance computing. When optimizing the performance of GEMM on GPU, the matrix is usually partitioned into a hierarchy of tiles to fit the thread hierarchy. In practice, the thread-level parallelism is affected not only by the tiling scheme but also by the resources that each tile consumes, such as registers and local data share memory. This paper presents a fine-grained prefetching scheme that improves the thread-level parallelism by balancing the usage of such resources. The gain and loss on instruction and thread level parallelism are analyzed and a mathematical model is developed to estimate the overall performance gain. Moreover, the proposed scheme is integrated into the open-source tool Tensile to automatically generate assembly and tune a collection of kernels to maximize the performance of DGEMM for a family of problem sizes. Experiments show about 1.10X performance speedup on a wide range of matrix sizes for both single and batched matrix-matrix multiplication.

关键词： Prefetching High performance computing Graphics processing units parallel processing Performance gain Mathematical models Libraries

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17th IEEE international Workshop on Automatic Performance Tuning (iWAPT2022)

17th IEEE International Workshop on Automatic Performance Tu...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Che-Rung Lee Satoshi Ohshima

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The goal of the Seventeenth international Workshop on Automatic Performance Tuning (iWAPT2022) is to bring together researchers who are investigating automated techniques for constructing and/or adapting algorithms and software for high-performance on modern complex machine architectures. iWAPT is a series of workshops that focus on research and techniques related to performance sustainability issues. The series provides an opportunity for researchers and users of automatic performance tuning (AT) technologies to exchange ideas and experiences acquired when applying such technologies to improve the performance of algorithms, libraries, and applications; in particular, on cutting edge computing platforms. The half-day workshops consist of presentations of research papers. Topics of interest include performance modeling; adaptive algorithms; autotuned numerical algorithms; libraries and scientific applications; empirical compilation; automated code generation; frameworks and theories of AT and software optimization; autonomic computing; and context-aware computing.

关键词： Conferences Tuning Software algorithms Software Libraries Sustainable development Scientific computing

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Resilience at Extreme Scale and Connections with Other Domains

Resilience at Extreme Scale and Connections with Other Domai...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Leonardo Bautista Gomez Barcelona Supercomputing Center Spain

Resilience has been one of the main research topics of the IPDPS community for decades. We have covered multiple types of failures and errors which has led to completely different fault tolerance techniques, some of them at the intersection of HPC and ML. The research work, carried out by researchers from many different institutions, shows a strong interaction between theoretical analysis and practical implementations. The results of this endeavor had led to many collaborations, publications and citations; but more interestingly, it has opened new questions and it has shown connections between HPC fields that we didn't know were connected before. In this talk, we will go over this trajectory and get a quick glance at what might come in the future for HPC resilience.

关键词： Resilience High performance computing Fault tolerant systems Fault tolerance distributed processing Trajectory Thyristors

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Retrospective: A Look Back at 20+Years of Experience in parallel computing Education 34

Retrospective: A Look Back at 20+Years of Experience in Para...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Adams, Joel C. Calvin Univ Dept Comp Sci Grand Rapids MI 49546 USA

ISBN: (纸本)9781728174457

The author has been teaching parallel computing since the late 1990s. This paper provides a brief history of some of the key experiences in his journey as a parallel computing educator, including formative faculty development workshops, technology shifts, NSF-sponsored projects, and courses taught. By reading this history, the reader may see how much has changed over the past two decades, and so gain insight into how to prepare for changes to parallel computing education in the future.

关键词： beowulf cluster computer science education high performance history multicore parallel software supercomputing

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distributed Algorithms for the Graph Biconnectivity and Least Common Ancestor Problems

Distributed Algorithms for the Graph Biconnectivity and Leas...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Ian Bogle George M. Slota Computer Science Department Rensselaer Polytechnic Institute Troy NY

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Graph connectivity analysis is one of the primary ways to analyze the topological structure of social networks. Graph biconnectivity decompositions are of particular interest due to how they identify cut vertices and cut edges in a network. We present the first, to our knowledge, implementation of a distributed-memory parallel biconnectivity algorithm. As part of our algorithm, we also require the computation of least common ancestors (LCAs) of non-tree edge endpoints in a BFS tree. As such, we also propose a novel distributed algorithm for the LCA problem. Using our implementations, we observe up to a 14.8× speedup from 1 to 128 MPI ranks for computing a biconnectivity decomposition.

关键词： distributed processing Social networking (online) Conferences distributed algorithms

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