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ESSA 2022 Keynote Speaker: Keep Your Composure: HPC, Data Services, and the Mochi Project

ESSA 2022 Keynote Speaker: Keep Your Composure: HPC, Data Se...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Rob Ross Mathematics and Computer Science Division Argonne National Laboratory

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

For decades high-performance computing (HPC) systems have been technology leaders in utilization of massive concurrency, in no small part because HPC applications are composed of software components that provide only the communication, concurrency, and synchronization needed for the task at hand. The storage community has likewise benefited from adopting this philosophy in recent years. The composable storage technology produced by the Mochi team is now widely leveraged in the DOE community as well as industry products, and academic and international research projects. In this talk we will cover the motivation for and roots of the Mochi framework, a variety of ways these tools are employed in HPC today, and consider new challenges to be tackled to extend the capabilities and reach of data services in HPC.

关键词： High performance computing Conferences Concurrent computing Computer science Task analysis System software Synchronization

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AITurbo: Unified Compute Allocation for Partial Predictable Training in Commodity Clusters 21

AITurbo: Unified Compute Allocation for Partial Predictable ...

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30th international symposium on High-Performance parallel and distributed computing (HPDC)

作者： Zhao, Laiping Li, Fangshu Qu, Wenyu Zhan, Kunlin Zhang, Qingman Tianjin Univ Coll Intelligence & Comp CIC Tianjin Key Lab Adv Networking TANKLAB Tianjin Peoples R China Tianjin Univ TANKLAB CIC Tianjin Peoples R China 58 Com Beijing Peoples R China UNICLOUD Tianjin Peoples R China

ISBN: (纸本)9781450382175

As the scale and complexity of deep learning models continues to grow, model training is becoming an expensive job and only a small number of well-financed organizations can afford. Are the resources in commodity clusters well utilized for training? or how much potential space are still there for further improving the training efficiency in commodity clusters? is an urgent question to answer. In this paper, we review the processing of distributed learning training (DDL) in commodity GPU clusters and find that the current resource utilization is not only low but also imbalanced. We observe two features that can be exploited for further improving the training efficiency: partial predictable training and unified CPU-GPU training. Based on the observations, we present AITurbo, a novel resource scheduler that treats predictable and unpredictable jobs separately, but allocates heterogeneous CPU-GPU resource in a unified way. For predictable jobs, AITurbo designs a predicting model to estimate their performance under various heterogeneous resource allocations. For unpredictable jobs, it schedules them following the least-attained-service-first manner. AITurbo further designs a Borda-count based multi-level feedback queue method to combine them together. AITurbo demonstrates that there is still significant space for improving the training efficiency in commodity clusters. We evaluate AITurbo using jobs from Tensorflow benchmarks, which are submitted following the real trace of three production systems. Experimental results show that, compared with the state-of-the-art, AITurbo can reduce the average job completion time of DDL jobs by 3x.

关键词： Scheduling distributed deep learning partial predictable training heterogeneous resource

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An Exploratory Study of Deep Learning for Predicting Computational Tasks Behavior in HPC Systems

An Exploratory Study of Deep Learning for Predicting Computa...

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international symposium on Computer Architecture and High Performance computing Workshops (SBAC-PADW)

作者： Alexandre H.L. Porto Micaella Coelho Kary Ocaña Carla Osthoff Francieli Boito Douglas O. Cardoso National Laboratory for Scientific Computing Petrópolis Brazil CNRS LaBRI University of Bordeaux Bordeaux INP INRIA Talence France Smart Cities Research Center Polytechnic Institute of Tomar Tomar Portugal

The scientific gateway BioinfoPortal for bioinformatics applications is hosted in the National Laboratory for Scientific computing (LNCC) and is coupled to the Santos Dumont (SDumont) supercomputer environment. BioinfoPortal offers a catalog of bioinformatics software that benefits from the parallel and distributed architecture offered by LNCC. Task submissions consume SDumont nodes shared by other users of the supercomputer; thus, it is important they use the best configuration, which is defined as the best choice of the number of threads/nodes to be allocated for every task submission. This article presents an analysis using neural networks to estimate the computational time required to execute bioinformatics software in several scenarios using a pre-configured number of nodes and threads. Our goal is to demonstrate the performance behavior of software such as RAxML in Bioinfoportal, and which computational scenario can be chosen to efficiently execute software in SDumont. Results support that the neural networks are adequate to predict the variable elapsed time, Elapsed, to evaluate the relationships between input parameters, number of bootstraps (RAxML), number of threads, and number of nodes, and to identify the fastest configuration. The goal is to make BioinfoPortal a smart, efficient, and green gateway. In future studies, we propose to study more variables and predictors as well as other bioinformatics software in BioinfoPortal.

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parallelizing and Balancing Coupled DSMC/PIC for Large-scale Particle Simulations

Parallelizing and Balancing Coupled DSMC/PIC for Large-scale...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Haozhong Qiu Chuanfu Xu Dali Li Haoyu Wang Jie Li Zheng Wang College of Computer National University of Defense Technology College of Aerospace Science and Engineer National University of Defense Technology School of Computing University of Leeds

In high-performance and parallel computing, an important application class is particle simulation. Due to massive particle migration among distributed simulation workers across simulation iterations, achieving balanced runtime work distribution is vital for accelerating large-scale realistic particle simulations. This paper proposes a novel approach to enable dynamic load balance for distributed numerical particle simulations, specifically targeting the latest coupled DSMC/PI C method. Unlike prior work, our approach adopts a dual, nested unstructured grid organization to facilitate coupled DSMC/PIC computation and runtime grid distribution. Our implementation leverages both centralized and distributed communication strategies to dynamically migrate particles among arbitrary parallel processes. It then employs a load balancer - driven by a carefully designed analytical model and a grid remapping mechanism - to dynamically redistribute the simulation workloads among parallel simulation workers. By constantly monitoring and redis-tributing the simulation work across workers, our approach can adapt to the change of particle distribution across simulation iterations, avoiding a few workers becoming the performance bottleneck of the entire simulation process. We integrate our techniques into a coupled DSMC/PIC solver and apply them to simulate the plasma plume with hydrogen atoms and ions. Experimental results show that our approach can scale well up to 1500+ processes with billions of particles, exhibiting the state-of-the-art parallel simulation scalability and efficiency for plasma plume simulation.

关键词： Adaptation models Analytical models Solid modeling Runtime Three-dimensional displays Computational modeling Numerical models

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Adaptive Hybrid FFT: A Novel Pipeline and Memory-Based Architecture for Radix-2k FFT in Large Size Processing

Adaptive Hybrid FFT: A Novel Pipeline and Memory-Based Archi...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Fangyu Zhao Chunhua Xiao Zhiguo Wang Xiaohua Du Bo Dong College of Computer Science Chongqing University Chongqing China Key Laboratory of Dependable Service Computing in Cyber Physical Society Ministry of Education China Sichuan Huacun Zhigu Technology Co. Ltd. Chengdu China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

In the field of digital signal processing, the fast Fourier transform (FFT) is a fundamental algorithm, with its processors being implemented using either the pipelined architecture, well-known for high-throughput applications but weak in hardware utilization, or the memory-based architecture, designed for area-constrained scenarios but failing to meet stringent throughput requirements. Therefore, we propose an adaptive hybrid FFT, which leverages the strengths of both pipelined and memory-based architectures. In this paper, we propose an adaptive hybrid FFT processor that combines the advantages of both architectures, and it has the following features. First, a set of radix-2 k multi-path delay commutators (MDC) units are developed to support high-performance large-size processing. Second, a conflict-free memory access scheme is formulated to ensure a continuous data flow without data contention. Third, We demonstrate the existence of a series of bit-dimension permutations for reordering input data, satisfying the generalized constraints of variable-length, high-radix, and any level of parallelism for wide adaptivity. Furthermore, the proposed FFT processor has been implemented on a field-programmable gate array (FPGA). As a result, the proposed work outperforms conventional memory-based FFT processors by requiring fewer computation cycles. It achieves higher hardware utilization than pipelined FFT architectures, making it suitable for highly demanding applications.

关键词： Program processors Fast Fourier transforms Memory architecture Pipelines Signal processing algorithms Throughput Hardware Delays Commutators Field programmable gate arrays

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Sparsity-Aware Tensor Decomposition

Sparsity-Aware Tensor Decomposition

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international symposium on parallel and distributed Processing (IPDPS)

作者： Sü reyya Emre Kurt Saurabh Raje Aravind Sukumaran-Rajam P. Sadayappan School of Computing University of Utah Salt Lake City Utah Department of EECS Washington State University Pullman Washington

Sparse tensor decomposition, such as Canonical Polyadic Decomposition (CPD), is a key operation for data analytics and machine learning. Its computation is dominated by a set of MTTKRP (Matricized Tensor Times Khatri Rao Product) operations. The collection of required MTTKRP operations for sparse CPD include common sub-computations across them and many approaches exist to factorize and reuse common sub-expressions. Prior work on sparse CPD has focused on minimizing the number of high-level operators. In this paper, we consider a design space that covers whether the partial MTTKRP results should be saved, different mode permutations and model the total volume of data movement to/from memory. Also, we propose a fine-grained load balancing method that supports higher levels of parallelization.

关键词： Solid modeling distributed processing Tensors Data analysis Machine learning Load management Data models

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(CGRA4HPC) 2022 Invited Speaker: Pushing the Boundaries of HPC with the Integration of AI

(CGRA4HPC) 2022 Invited Speaker: Pushing the Boundaries of H...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Raghu Prabhakar SambaNova Systems

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

As the market for high-performance computing continues to heat up there are constraints caused by the limited processing speed capacity of current architectures like CPUs and GPUs. Higher-resolution image processing requires massive computational capabilities making it challenging and costly for even the most innovative companies to succeed. SambaNova Systems has pioneered the ability to liberate organizations from the limitations of their legacy solutions — providing the core datacenter infrastructure to quickly build and deploy AI technologies at scale. Developers can run a 100-billion parameter model with ease, and enable highperformance processing of complex structures such as high-resolution images, pushing computer vision boundaries far beyond 4k. SambaNova Systems will showcase groundbreaking technology delivered by SambaNova's Reconfigurable Dataflow Architecture™ - an accelerated computing architecture designed to efficiently execute a broad range of AI and HPC applications.

关键词： Computer architecture Artificial intelligence distributed processing Conferences Image processing High performance computing Heating systems

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12th IEEE international Workshop on Accelerators and Hybrid Emerging Systems

12th IEEE International Workshop on Accelerators and Hybrid ...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Lena Oden

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The current computing landscape has gone through an ever-increasing rate of change and innovation. This change has been driven by the relentless need to improve the energy-efficient, memory, and compute throughput at all levels of the architectural hierarchy. Although the amount of data that has to be organized by today's systems posed new challenges to the architecture, which can no longer be solved with classical, homogeneous design. Improvements in all of those areas have led Heterogeneous systems to become the norm rather than the exception.

关键词： Conferences Computer architecture distributed processing Artificial intelligence Market research Heterogeneous networks Graphics processing units

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The Fast and Scalable MPI Application Launch of the Tianhe HPC system

The Fast and Scalable MPI Application Launch of the Tianhe H...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Yiqin Dai Yong Dong Min Xie Kai Lu Ruibo Wang Mingtian Shao Juan Chen College of Computer National University of Defense Technology Changsha China

Fast and scalable MPI application launch helps achieve exascale performance and is becoming a common goal in high-performance computing. However, the traditional launch technique suffers from scalability deficiencies in the global information exchange and the global barrier operation. This drawback makes it challenging to launch MPI applications quickly in large-scale systems. In this paper, we propose a fast and scalable application launch technique and details its associated hardware and software support. The optimized launch technique includes a locality-aware static address generation rule for eliminating the need for address exchange and a topology-aware global communication scheme for improving global communication efficiency. We also propose an optimized application launch sequence for supporting the above launch technique. We implement and evaluate the proposed launch technique on the Tianhe-2A supercomputer and the Tianhe Exascale Prototype Upgrade System. Experimental results show that our technique can reduce the launch time by 26.1% when launching an application with 256K processes.

关键词： Costs Scalability High performance computing Prototypes Supercomputers Software Hardware

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Resource Utilization Aware Job Scheduling to Mitigate Performance Variability

Resource Utilization Aware Job Scheduling to Mitigate Perfor...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Daniel Nichols Aniruddha Marathe Kathleen Shoga Todd Gamblin Abhinav Bhatele Department of Computer Science University of Maryland College Park Maryland USA Lawrence Livermore National Laboratory Livermore California USA

Resource contention on high performance computing (HPC) platforms can lead to significant variation in application performance. When several jobs experience such large variations in run times, it can lead to less efficient use of system resources. It can also lead to users over-estimating their job's expected run time, which degrades the efficiency of the system scheduler. Mitigating performance variation on HPC platforms benefits end users and also enables more efficient use of system resources. In this paper, we present a pipeline for collecting and analyzing system and application performance data for jobs submitted over long periods of time. We use a set of machine learning (ML) models trained on this data to classify performance variation using current system counters. Additionally, we present a new resource-aware job scheduling algorithm that utilizes the ML pipeline and current system state to mitigate job variation. We evaluate our pipeline, ML models, and scheduler using various proxy applications and an actual implementation of the scheduler on an Infiniband-based fat-tree cluster.

关键词： Measurement Schedules distributed processing Scheduling algorithms High performance computing Pipelines Machine learning

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