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Implementing an Attack Graph Generator in CUDA 34

Implementing an Attack Graph Generator in CUDA

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Li, Ming Hawrylak, Peter J. Hale, John Univ Tulsa Tandy Sch Comp Sci Tulsa OK 74104 USA

ISBN: (纸本)9781728174457

Attack graphs can be used in security analysis for both computer networks and cyber physical systems to enumerate all possible attack paths. The main challenge in applying attack graphs is the design of scalable generators, which should construct large scale graphs within practical limits for execution time and storage resources. With the availability of high performance computing hardware, parallel computing units can be employed to accelerate the exploration of new states in attack graph generation. While NVIDIA's GPU devices have significantly improved the performance of other graph-oriented algorithms, there is little research using them on the generation of attack graphs. In this paper, we present a parallel attack graph generator based on NVIDIA's extension of C language: CUDA. To accelerate the exploration, the generator uses a large number of warps in the GPU device. Each warp is assigned with multiple initial states, which are then expanded by 32 in-warp threads. The performance experiments are conducted on a virtual machine instance providing a Tesla P4 GPU. The acceleration achieved demonstrates the effectiveness of using a large number of CUDA cores to accelerate the attack graph generator.

关键词： Cyber security attack graph parallel computing NVIDIA GPU CUDA

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Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA 34

Performance Evaluation of Pipelined Communication Combined w...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Fujita, Norihisa Kobayashi, Ryohei Yamaguchi, Yoshiki Ueno, Tomohiro Sano, Kentaro Boku, Taisuke Univ Tsukuba Ctr Computat Sci Tsukuba Ibaraki Japan Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki Japan RIKEN Ctr Computat Sci Kobe Hyogo Japan

ISBN: (纸本)9781728174457

In recent years, much High Performance computing (HPC) researchers attract to utilize Field Programmable Gate Arrays (FPGAs) for HPC applications. We can use FPGAs for communication as well as computation thanks to FPGA's I/O capabilities. HPC scientists cannot utilize FPGAs for their applications because of the difficulty of the FPGA development, however High Level Synthesis (HLS) allows them to use with appropriate costs. In this study, we propose a Communication Integrated Reconfigurable computing System (CIRCUS) to enable us to utilize high-speed interconnection of FPGAS from OpenCL. CIRCUS makes a fused single pipeline combining the computation and the communication, which hides the communication latency by completely overlapping them. In this paper, we present the detail of the implementation and the evaluation result using two benchmarks: pingpong benchmark and allreduce benchmark.

关键词： FPGA OpenCL HLS parallel computing inter-connection

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Benchmarking Quantum Processor Performance through Quantum Distance Metrics Over An Algorithm Suite

Benchmarking Quantum Processor Performance through Quantum D...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Samuel Stein Nathan Wiebe James Ang Ang Li Pacific Northwest National Laboratory Richland WA USA

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Quantum computing is poised to solve computational paradigms that classical computing could never feasibly reach. Tasks such as prime factorization to Quantum Chemistry are examples of classically difficult problems that have analogous algorithms that are sped up on quantum computers. To attain this computational advantage, we must first traverse the noisy intermediate scale quantum (NISQ) era, in which quantum processors suffer from compounding noise factors that can lead to unreliable algorithm induction producing noisy results. We describe QASMBench, a suite of QASM-level (Quantum assembly language) benchmarks that challenge all realisable angles of quantum processor noise. We evaluate a large portion of these algorithms by performing density matrix tomography on 14 IBMQ Quantum devices.

关键词： Performance evaluation Computers distributed processing Program processors Quantum chemistry Conferences Benchmark testing

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Teaching Modern Multithreading in CS2 with Actors 34

Teaching Modern Multithreading in CS2 with Actors

引用

34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Lewis, Mark C. Lacher, Lisa L. Trinity Univ Dept Comp Sci San Antonio TX 78212 USA Univ Houston Clear Lake Dept Comp Sci Houston TX USA

ISBN: (纸本)9781728174457

Explosive growth in multiprocessor computing and the pervasive nature of multicore processors has not only made multithreading and related topics such as parallelism, concurrency, synchronization, etc. an essential part of any undergraduate Computer Science curriculum, it has also lead to the addition of newer constructs to support multithreading in many languages. Not only is it important to motivate student interest in this topic, it is important that they are also educated in current methods used in industry. This can mean an increase in material that needs to be covered. Because of the increase in scope of a CS education, teaching topics in parallel and distributed computing in a hands-on manner is challenging, thus it is valuable for educators to explore different methods of educational delivery in order to best engage their students within the limits of curriculum timelines. The actor model is immensely popular in industry and runs some of the most important software today. In this paper, we describe how we are using Actors as a significant part of the multithreading coverage at the CS2 level, for first-year computer science majors. We also describe a semesterlong project that involves the use of these concepts to help solidify student understanding and present student feedback on the project and approach.

关键词： Computer Science Education parallel and distributed computing multithreading actors futures Scala

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Nonblocking execution in GraphBLAS

Nonblocking execution in GraphBLAS

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Aristeidis Mastoras Sotiris Anagnostidis Albert– Jan N. Yzelman Computing Systems Laboratory Zurich Research Center Huawei Technologies Switzerland Data Analytics Laboratory Department of Computer Science ETH Zurich Switzerland

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

GraphBLAS is a recent standard that allows the expression of graph algorithms in the language of linear algebra and enables automatic code parallelization and optimization. GraphBLAS operations are executed either in blocking or in non-blocking mode. Although there exist multiple implementations of GraphBLAS for efficient blocking execution on both shared-and distributed-memory systems, none of these implementations supports full nonblocking execution to improve data locality. In this paper, we present a preliminary evaluation for two algorithms, Pagerank and Conjugate Gradient, that confirms the importance of nonblocking execution, by showing promising speedups over the corresponding blocking execution.

关键词： Analytical models distributed processing Heuristic algorithms Instruction sets distributed databases Manuals Linear algebra

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Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs distributed Systems 34

Hardware resources analysis of BNNs splitting for FARD-based...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Fiscaletti, Giorgia Speziali, Marco Stornaiuolo, Luca Santambrogio, Marco D. Sciuto, Donatella Politecn Milan Dipartimento Elettron Informaz & Bioingn DEIB Milan Italy

ISBN: (纸本)9781728174457

FPGAs have proven to be valid architectures to accelerate the inference phase of Convolutional Neural Networks (CNNs). State-of-the-art works also demonstrated that it is possible to take advantage of a distributed FPGA-base system to improve performance, power consumption and scalability of such algorithms. However, the hardware resource usage, communication, and the nodes management become main aspects when dealing with an embedded distributed scenario. In this context, FINN optimizes the FPGA-based CNNs with binarization and FARD is a framework that allows the acceleration of fog computing-based application with FPGAs. In this work, we present how to extend FARD to deal with job-based applications rather than the event-based fog computing scenario. In particular, we analyzed two PYNQ-Z1 connected each other and we implemented a distributed BNN algorithm based on FINN's CnvW2A2. Results show how hardware resources vary according to the division of the network when splitting after each convolutional layer.

关键词： Binarized Neural Networks BNN PYNQ embedded distributed

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An Efficient Ambient Noise Cross-Correlation Algorithm on Heterogeneous CPU-GPU Cluster

An Efficient Ambient Noise Cross-Correlation Algorithm on He...

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international symposium on parallel Architectures, Algorithms and Programming (PAAP)

作者： Chao Wu Xing Tan Huikun Li Guangzhong Sun Network and Information Center Supercomputing Center University of Science and Technology of China Hefei China School of Earth and Space Sciences University of Science and Technology of China Hefei China School of Software Engineering University of Science and Technology of China Hefei China School of Computer Science and Technology University of Science and Technology of China Hefei China

ISBN: (纸本)9781665452199

Calculation of noise cross-correlation functions (NCF) plays a vital role in ambient noise seismology. However high computation and storage requirements of NCF become huge obstacles in development of ambient noise seismology. Nowadays heterogeneous clusters show great impact in scientific computing. In this paper, we propose a parallel NCF algorithm based on heterogeneous cluster. Firstly, input SAC files are partitioned by dimension of dates and distributed to different nodes of heterogeneous cluster. Secondly, during NCF computation in each node, workloads are divided by station pairs, and calculated in different graphics processing units (GPUs) embedded in computing node. Finally, all NCF results of different dates are gathered to one computing node and stacked using all central processing units (CPUs) of that node. Experimental results demonstrate that the parallel NCF computing can be accomplished within much less time than that of the CPU counterpart, and the speedup remains almost linear when increasing number of computing nodes.

关键词： Correlation Scientific computing Seismology Clustering algorithms Graphics processing units Programming parallel processing

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A Family of Fast parallel Greedy Algorithms for the Steiner Forest Problem

A Family of Fast Parallel Greedy Algorithms for the Steiner ...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Laleh Ghalami Daniel Grosu Department of Computer Science Wayne State University Detroit USA

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

We introduce a family of fast parallel greedy algorithms for the Steiner Forest Problem, a fundamental combinatorial optimization problem in graphs. Given an undirected graph with non-negative weights for edges and a set of pairs of vertices called terminals, the Steiner Forest Problem is to find the minimum cost subgraph that connects each of the terminal pairs together. We design a family of parallel algorithms based on a sequential heuristic greedy algorithm called Paired Greedy which iteratively connects the terminal pairs that have the minimum distance. The family of parallel algorithms consists of a set of algorithms exhibiting various degrees of parallelism determined by the number of pairs that are connected in parallel in each iteration of the algorithms. We implement and run the algorithms on a multi-core system and perform an extensive experimental analysis. The results show that our proposed parallel algorithms achieve significant speedup with respect to the sequential Paired Greedy algorithm and provide solutions with costs that are very close to those of the solutions obtained by the sequential Paired Greedy algorithm.

关键词： Greedy algorithms Measurement Concurrent computing distributed processing Costs Conferences Forestry

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Development and benchmarking a parallel Data AcQuisition framework using MPI with hash and hash plus tree structures in a cluster environment 19

Development and benchmarking a parallel Data AcQuisition fra...

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19th international symposium on parallel and distributed computing (ISPDC)

作者： Czarnul, Pawel Golaszewski, Grzegorz Jereczek, Grzegorz Maciejewski, Maciej Gdansk Univ Technol Fac Elect Telecommun & Informat Narutowicza 11-12 PL-80233 Gdansk Poland Intel Technol Poland Slowackiego 173 PL-80298 Gdansk Poland

ISBN: (纸本)9781728189468

In the paper we propose a solution that uses either a 3-layered index structure based on hash tables or a hash+tree structure for efficient parallel processing of data in a Data AcQuisition (DAQ) system. The proposed framework allows for parallel data writes from multiple multithreaded client processes to multiple multithreaded server processes that use a thread-safe hash-table-based library. Communication is conducted using an MPI_THREAD_MULTIPLE enabled MPI implementation. We demonstrate that the solution scales well in two cluster configurations using InfiniBand, specifically for increasing numbers of client as well as server threads. We present how performance depends on various configuration parameters of a DAQ systems like data distribution across the readout system, its size, and percentage of data to be fetched. Furthermore, we show how it depends on the size of value associated with a given write/read. We compare the performance of both proposed data structures for different configurations. The results allow the reader to learn real performance numbers and characteristics of such a solution, applicable to large scale parallel data processing in a DAQ system and choose the optimal solution.

关键词： Data AcQuisition (DAQ) system parallel processing scalability Message Passing Interface

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A General Offloading Approach for Near-DRAM Processing-In-Memory Architectures

A General Offloading Approach for Near-DRAM Processing-In-Me...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Dan Chen Hai Jin Long Zheng Yu Huang Pengcheng Yao Chuangyi Gui Qinggang Wang Haifeng Liu Haiheng He Xiaofei Liao Ran Zheng National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Clusters and Grid Computing Lab Huazhong University of Science and Technology China

Processing-in-memory (PIM) is promising to solve the well-known data movement challenge by performing in-situ computations near the data. Leveraging PIM features is pretty profitable to boost the energy efficiency of applications. Early studies mainly focus on improving the programmability for computation offloading on PIM architectures. They lack a comprehensive analysis of computation locality and hence fail to accelerate a wide variety of applications. In this paper, we present a general-purpose instruction-level offloading technique for near-DRAM PIM architectures, namely IOTPIM, to exploit PIM features comprehensively. IOTPIM is novel with two technical advances: 1) a new instruction offloading policy that fully considers the locality of the whole on-chip cache hierarchy, and 2) an offloading performance benefit prediction model that directly predicts offloading performance benefits of an instruction based on the input dataset characterizes, preserving low analysis overheads. The evaluation demonstrates that IOTPIM can be applied to accelerate a wide variety of applications, including graph processing, machine learning, and image processing. IOT-PIM outperforms the state-of-the-art PIM offloading techniques by 1.28×-1.51× while ensuring offloading accuracy as high as 91.89% on average.

关键词： Analytical models Technological innovation distributed processing Systematics Image processing Computer architecture Machine learning

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