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Deep Learning Optimization for Many-Core Virtual Platforms 1

11th international symposium on parallel Architectures, Algorithms and Programming, PAAP 2020

作者： Cai, Hengyu Ning, Chengming Zheng, Qilong University of Science and Technology of China Hefei China AnHui Province Key Laboratory of High Performance Computing Hefei China

ISBN: (数字)9789811600104

ISBN: (纸本)9789811600098

The rapid development of deep learning technology has made deep learning models widely used in image processing, speech recognition, and target tracking. However, the model becomes larger and larger, and it is difficult to deploy on a stand-alone device, usually on a distributed computing platform. As a high-performance digital signal processor developed by the 38th Research Institute of China Electronics Technology Group, HXDSP has strong computing power and rich computing resources, and is suitable for computing-intensive applications such as deep learning. Design the many-core virtual platform based on the HXDSP simulator, and provide the parallel communication interface MPIRIO to realize fast communication and task synchronization between the HXDSPs, and provide basic conditions for the deployment of deep learning models. At the same time, the parallel computing capability and pipeline mechanism provided by the virtual platform are used to accelerate the operation of the model. Aiming at the problem that the traditional gradient descent algorithm needs to be manually set, the meta-learning optimization algorithm is used to realize the adaptive fine-tuning of the model on the virtual platform, forming a deep learning optimization framework based on the CPU/HXDSP heterogeneous system. © 2021, Springer Nature Singapore Pte Ltd.

关键词： Digital signal processors

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Memory-Aware Scheduling of Tasks Sharing Data on Multiple GPUs with Dynamic Runtime Systems

Memory-Aware Scheduling of Tasks Sharing Data on Multiple GP...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Maxime Gonthier Loris Marchal Samuel Thibault ENS-Lyon France University of Bordeaux France

The use of accelerators such as GPUs has become mainstream to achieve high performance on modern computing systems. GPUs come with their own (limited) memory and are connected to the main memory of the machine through a bus (with limited bandwidth). When a computation is started on a GPU, the corresponding data needs to be transferred to the GPU before the computation starts. Such data movements may become a bottleneck for performance, especially when several GPUs have to share the communication bus. Task-based runtime schedulers have emerged as a convenient and efficient way to use such heterogeneous platforms. When processing an application, the scheduler has the knowledge of all tasks available for processing on a GPU, as well as their input data dependencies. Hence, it is able to choose which task to allocate to which GPU and to reorder tasks so as to minimize data movements. We focus on this problem of partitioning and ordering tasks that share some of their input data. We present a novel dynamic strategy based on data selection to efficiently allocate tasks to GPUs and a custom eviction policy, and compare them to existing strategies using either a well-known graph partitioner or standard scheduling techniques in runtime systems. We also improved an offline scheduler recently proposed for a single GPU, by adding load balancing and task stealing capabilities. All strategies have been implemented on top of the STARPU runtime, and we show that our dynamic strategy achieves better performance when scheduling tasks on multiple GPU s with limited memory.

关键词： distributed processing Runtime Graphics processing units distributed databases Bandwidth Dynamic scheduling Load management

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parallel computing and Optimization of Lattice Boltzmann Method Based on SW26010 Processor 18

Parallel Computing and Optimization of Lattice Boltzmann Met...

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18th IEEE Int Symp on parallel and distributed Proc with Applicat (ISPA) / 10th IEEE Int Conf on Big Data and Cloud Comp (BDCloud) / IEEE Int Symp on Social Comp and Networking (SocialCom) / IEEE Int Conf on Sustainable Comp and Commun (SustainCom)

作者： Zhang, Xiaoxiao Wang, Liangjun Chu, Xuesen Ding, Hu Zhang, Wu Shanghai Univ Sch Comp Engn & Sci Shanghai Peoples R China Shanghai Univ Informat Off Shanghai Peoples R China Natl Supercomp Ctr Wuxi Applicat Software Dept Wuxi Jiangsu Peoples R China Shanghai Univ Sch Mech & Engn Sci Shanghai Inst Appl Math & Mech Shanghai Peoples R China

ISBN: (纸本)9781665414852

The Lattice Boltzmann Method (LBM) is an important and powerful approach in computational fluid dynamics, particularly for large-scale parallel computing of complicated flows, such as flow noise simulations. The parallel computing, including both algorithm and programming of LBM, is studied and implemented on the Sunway TaihuLight supercomputer cluster with the peak speed of 100Pflops in this paper. Furthermore, we adopt two parallel modes, Message Passing Interface (MPI) parallel mode and athread parallel mode, to optimize the LBM parallel computing performance by considering the structure of the SW26010 processor. Finally, we conduct large-scale numerical experiments and detailed parallel performance evaluation for different cases based on 30P30N airfoil. The results show that the present algorithm has excellent speedup and scalability in different computational scales and cores.

关键词： Lattice Boltzmann Method parallel optimization synchronization optimization strategy 30P30N airfoil SW26010 processor

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StragglerHelper: Alleviating Straggling in computing Clusters via Sharing Memory Access Patterns 34

StragglerHelper: Alleviating Straggling in Computing Cluster...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Liu, Wenjie Huang, Ping He, Xubin Temple Univ Dept Comp & Informat Sci Philadelphia PA 19122 USA

ISBN: (纸本)9781728168760

Clusters have been a prevalent and successful computing framework for processing large amount of data due to their distributed and parallelized working paradigm. A task submitted to a cluster is typically divided into a number of subtasks which are designated to different work nodes running the same code but dealing with different equal portion of the dataset to be processed. Due to the existence of heterogeneity, it could easily result in stragglers unfairly slowing down the entire processing, because work nodes finish their subtasks at different rates. In this study, we aim to speed up straggling work nodes to quicken the overall processing by leveraging exhibited performance variation. More specifically, we propose StragglerHelper which conveys the memory access characteristics experienced by the forerunner to the stragglers such that stragglers can be sped up due to the accurately informed memory prefetching. A Progress Monitor is deployed to supervise the respective progresses of the work nodes and inform the memory access patterns of forerunner to straggling nodes. Our evaluation results with the SPEC MPI 2007 and BigDataBench on a cluster of 64 work nodes have shown that StragglerHelper is able to improve the execution time of stragglers by up to 99.5% with an average of 61.4%, contributing to an overall improvement of the entire cohort of the cluster by up to 46.7% with an average of 9.9% compared to the baseline cluster.

关键词： Cluster Memory straggler mitigation performance variation

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GradedDAG: An Asynchronous DAG-based BFT Consensus with Lower Latency

GradedDAG: An Asynchronous DAG-based BFT Consensus with Lowe...

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Reliable distributed Systems

作者： Xiaohai Dai Zhaonan Zhang Jiang Xiao Jingtao Yue Xia Xie Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China School of Computer Science and Technology Hainan University China

To enable parallel processing, the Directed Acyclic Graph (DAG) structure is introduced to the design of asyn-chronous Byzantine Fault Tolerant (BFT) consensus protocols, known as DAG-based BFT. Existing DAG-based BFT protocols operate in successive waves, with each wave containing three or four Reliable Broadcast (RBC) rounds to broadcast data, resulting in high latency due to the three communication steps required in each RBC. For instance, Tusk, a state-of-the-art DAG-based BFT protocol, has a good-case latency of 7 communication steps and an expected worst latency of 21 communication steps. To reduce latency, we propose GradedDAG, a new DAG-based BFT consensus protocol based on our adapted RBC called Graded RBC (GRBC) and the Consistent Broadcast (CBC), with each wave consisting of only one GRBC round and one CBC round. Through GRBC, a replica can deliver data with a grade of 1 or 2, and a non-faulty replica delivering the data with grade 2 can ensure that more than 2/3 of replicas have delivered the same data. Meanwhile, through CBC, data delivered by different non-faulty replicas must be identical. In each wave, a block in the GRBC round will be elected as the leader. If a leader block has been delivered with grade 2, it and all its ancestor blocks can be committed. GradedDAG offers a good-case latency of 4 communication steps and an expected worst latency of 7.5 communication steps, significantly lower than the state-of-the-art. Experimental results demonstrate GradedDAG's feasibility and efficiency.

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Integrating DOTS With Blockchain Can Secure Massive IoT Sensors 34

Integrating DOTS With Blockchain Can Secure Massive IoT Sens...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Badruddoja, Syed Dantu, Ram Widick, Logan Zaccagni, Zachary Upadhyay, Kritagya Univ North Texas Dept Comp Sci & Engn Denton TX 76207 USA

ISBN: (纸本)9781728174457

This paper presents a novel approach to securing IoT devices by leveraging DDoS Open Threat Signaling (DOTS) architecture on a Blockchain framework. Like many areas of the information technology domain, IoT sensors are also prone to attacks but on a larger scale. There are millions of devices being connected to a central domain to provide different types of services. Since these low-powered IoT devices have constrained technical requirements with less computational capabilities, they lack the capacity to judge their behavior as benign or malignant. IoT relies heavily on the higher level of intelligent nodes to decide on their status. An IoT Controller/Edge server handles the registration and the limited management of devices. Since traditional security is unable to protect the IoT environment sufficiently, we present a Blockchain-based DDoS detection approach to secure and mitigate such attacks in the IoT environment. Our test setup includes dataset from four sensors over two months. These values were tested using a threshold calculation against the variation of temperature, humidity, pressure, and wind direction on that day to find out whether an IoT sensor is under a DDoS attack. Our results show how DOTS can help in detection of attack when mapped on IoT edge computing.

关键词： Cybersecurity Blockchain IoT Edge computing distributed Ledger DDOS Protection Smart Contracts

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parallel algorithms for finding connected components using linear algebra

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JOURNAL OF parallel AND distributed computing 2020年 144卷 14-27页

作者： Zhang, Yongzhe Azad, Ariful Buluc, Aydin Grad Univ Adv Studies SOKENDAI Dept Informat Hayama Kanagawa Japan Indiana Univ Dept Intelligent Syst Engn Bloomington IN 47405 USA Lawrence Berkeley Natl Lab Computat Res Div Berkeley CA USA

Finding connected components is one of the most widely used operations on a graph. Optimal serial algorithms for the problem have been known for half a century, and many competing parallel algorithms have been proposed over the last several decades under various different models of parallel computation. This paper presents a class of parallel connected-component algorithms designed using linear-algebraic primitives. These algorithms are based on a PRAM algorithm by Shiloach and Vishkin and can be designed using standard GraphBLAS operations. We demonstrate two algorithms of this class, one named LACC for Linear Algebraic Connected Components, and the other named FastSV which can be regarded as LACC's simplification. With the support of the highly-scalable Combinatorial BLAS library, LACC and FastSV outperform the previous state-of-the-art algorithm by a factor of up to 12x for small to medium scale graphs. For large graphs with more than 50B edges, LACC and FastSV scale to 4K nodes (262K cores) of a Cray XC40 supercomputer and outperform previous algorithms by a significant margin. This remarkable performance is accomplished by (1) exploiting sparsity that was not present in the original PRAM algorithm formulation, (2) using high-performance primitives of Combinatorial BLAS, and (3) identifying hot spots and optimizing them away by exploiting algorithmic insights. (C) 2020 Elsevier Inc. All rights reserved.

关键词： Connected Component distributed memory GraphBLAS

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Automatic Selection of Tuning Plugins in PTF Using Machine Learning 34

Automatic Selection of Tuning Plugins in PTF Using Machine L...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Mijakovic, Robert Gerndt, Michael Bavarian Acad Sci & Humanities Leibniz Supercomp Ctr LRZ Garching Germany Tech Univ Munich Inst Informat Garching Germany

ISBN: (纸本)9781728174457

Performance tuning of scientific codes often requires tuning many different aspects like vectorization, OpenMP synchronization, MPI communication, and load balancing. The Periscope Tuning Framework (PTF), an online automatic tuning framework, relies on a flexible plugin mechanism providing tuning plugins for different tuning aspects. Individual plugins can be combined for convenience into meta-plugins. Since each plugin can take considerable execution time for testing various combination of the tuning parameters, it is desirable to automatically predict the tuning potential of plugins for programs before their application. We developed a generic automatic prediction mechanism based on machine learning techniques for this purpose. This paper demonstrates this technique in the context of the Compiler Flags Selection plugin, that tunes the parameters of a user specified compiler for a given application.

关键词： parallel computing performance tuning auto-tuning PTF program characterization machine learning

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CycLedger: A Scalable and Secure parallel Protocol for distributed Ledger via Sharding 34

CycLedger: A Scalable and Secure Parallel Protocol for Distr...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Zhang, Mengqian Li, Jichen Chen, Zhaohua Chen, Hongyin Deng, Xiaotie Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai 200240 Peoples R China Peking Univ Sch Elect Engn & Comp Sci Beijing 100871 Peoples R China

ISBN: (纸本)9781728168760

Traditional public distributed ledgers have not been able to scale-out well and work efficiently. Sharding is deemed as a promising way to solve this problem. By partitioning all nodes into small committees and letting them work in parallel, we can significantly lower the amount of communication and computation, reduce the overhead on each node's storage, as well as enhance the throughput of the distributed ledger. Existing sharding-based protocols still suffer from several serious drawbacks. The first thing is that all non-faulty nodes must connect well with each other, which demands a huge number of communication channels in the network. Moreover, previous protocols have faced great loss in efficiency in the case where the honesty of each committee's leader is in question. At the same time, no explicit incentive is provided for nodes to actively participate in the protocol. We present CycLedger, a scalable and secure parallel protocol for distributed ledger via sharding. Our protocol selects a leader and a partial set for each committee, who are in charge of maintaining intra-shard consensus and communicating with other committees, to reduce the amortized complexity of communication, computation, and storage on all nodes. We introduce a novel semi-commitment scheme between committees and a recovery procedure to prevent the system from crashing even when leaders of committees are malicious. To add incentive for the network, we use the concept of reputation, which measures each node's trusty computing power. As nodes with a higher reputation receive more rewards, there is an encouragement for nodes with strong computing ability to work honestly to gain reputation. In this way, we strike out a new path to establish scalability, security, and incentive for the sharding-based distributed ledger.

关键词： distributed Ledger Sharding Scalability Security Reputation

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An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic computing

An Efficient Data Structure for Sparse Bit-Vectors with Appl...

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international symposium on Advanced Research in Asynchronous Circuits and Systems

作者： Prafull Purohit Johannes Leugering Rajit Manohar Electrical Engineering Yale University New Haven CT United States Broadband and Broadcast Dept. Fraunhofer Institute for Integrated Circuits (IIS) Erlangen Germany

Iterating over all the elements of a set is a very common problem in highly parallel systems. In hardware, this is typically realized by either storing the set-membership of each element in a fixed-length bit-vector or by storing just the indices of the members in a dynamically sized queue. However, the former solution is only efficient in terms of memory and runtime if each element is a member of the set with approximately 50% probability, whereas the latter is only efficient if the set is extremely sparse. We propose an alternative asynchronous, concurrent, distributed data structure based on a binary tree topology that is more efficient for sets with sparsity in between these two extremes. The proposed structure allows us to construct a set by adding individual elements one at a time in arbitrary order, and to iterate over all these elements exactly once, clearing the set in the process. We analyzed this data structure, simulated its behavior in CHP, synthesized it into an asynchronous digital circuit, optimized the circuits, and performed SPICE simulation to evaluate our design. The results confirm that our proposed structure offers a low-latency, low-power solution for moderately sparse data, and may thus prove useful for asynchronous and neuromorphic systems.

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