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distributed Algorithms for the Graph Biconnectivity and Least Common Ancestor Problems 36

Distributed Algorithms for the Graph Biconnectivity and Leas...

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36th IEEE international parallel and distributed Processing symposium (IEEE IPDPS)

作者： Bogle, Ian Slota, George M. Rensselaer Polytech Inst Comp Sci Dept Troy NY 12180 USA

ISBN: (纸本)9781665497473

Graph connectivity analysis is one of the primary ways to analyze the topological structure of social networks. Graph biconnectivity decompositions are of particular interest due to how they identify cut vertices and cut edges in a network. We present the first, to our knowledge, implementation of a distributed-memory parallel biconnectivity algorithm. As part of our algorithm, we also require the computation of least common ancestors (LCAs) of non-tree edge endpoints in a BFS tree. As such, we also propose a novel distributed algorithm for the LCA problem. Using our implementations, we observe up to a 14.8 x speedup from 1 to 128 MPI ranks for computing a biconnectivity decomposition.

关键词： distributed processing Social networking (online) Conferences distributed algorithms

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distributed Multi-GPU Community Detection on Exascale computing Platforms

Distributed Multi-GPU Community Detection on Exascale Comput...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Sattar, Naw Safrin Lu, Hao Wang, Feiyi Halappanavar, Mahantesh Oak Ridge Natl Lab Oak Ridge TN 37830 USA Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9798350364613;9798350364606

Community detection is a fundamental operation in graph mining, and by uncovering hidden structures and patterns within complex systems it helps solve fundamental problems pertaining to social networks, such as information diffusion, epidemics, and recommender systems. Scaling graph algorithms for massive networks becomes challenging on modern distributed-memory multi-GPU (Graphics Processing Unit) systems due to limitations such as irregular memory access patterns, load imbalances, higher communication-computation ratios, and cross-platform support. We present a novel algorithm HiPDPL-GPU (distributed parallel Louvain) to address these challenges. We conduct experiments involving different partitioning techniques to achieve an optimized performance of HiPDPL-GPU on the two largest supercomputers: Frontier and Summit. Remarkably, HiPDPL-GPU processes a graph with 4.2 billion edges in less than 3 minutes using 1024 GPUs. Qualitatively, the performance of HiPDPL-GPU is similar or better compared to other state-of-the-art CPU- and GPU-based implementations. While prior GPU implementations have predominantly employed CUDA, our first-of-its-kind implementation for community detection is cross-platform, accommodating both AMD and NVIDIA GPUs.

关键词： multi-GPU Louvain community detection clustering hybrid HIP MPI

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MLF: Multi-level forwarding based on EdgeMesh in edge computing environment 22

MLF: Multi-level forwarding based on EdgeMesh in edge comput...

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22nd IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2024

作者： Wei, Xin Li, Xin Nanjing University of Aeronautics and Astronautics Nanjing China

ISBN: (纸本)9798331509712

KubeEdge is a widely used edge computing system. It ensures quality of service through multi-replica deployment, horizontal scaling, etc. EdgeMesh, provided by KubeEdge, can offer key functions such as edge service discovery, cross-subnet communication, load balancing, etc. However, the native load balancing policies provided by EdgeMesh do not consider the wide geographic distribution of edge nodes. It forwards user requests to each application replica on all nodes, leading to higher end-to-end latency and lower ***, we propose a multi-level forwarding (MLF) policy based on EdgeMesh. The MLF divides the edge nodes close to each other into the same cluster. Request forwarding within the same cluster is called intra-cluster forwarding while forwarding between different clusters is called extra-cluster forwarding. It prioritizes processing user requests locally, then considers forwarding the requests to another node to process in the intra-cluster, and finally selects the best extra-cluster node for forwarding and processing. Our experimental evaluation results show that MLF can effectively reduce the end-to-end latency and improve the application throughput in edge computing scenarios compared to EdgeMesh's default load balancing policies. © 2024 IEEE.

关键词： Quality of service

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Combined Application of Approximate computing Techniques in DNN Hardware Accelerators 36

Combined Application of Approximate Computing Techniques in ...

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36th IEEE international parallel and distributed Processing symposium (IEEE IPDPS)

作者： Russo, Enrico Palesi, Maurizio Patti, Davide Lahdhiri, Habiba Monteleone, Salvatore Ascia, Giuseppe Catania, Vincenzo Univ Catania Catania Italy Niccolo Cusano Univ Rome Italy ESIEE Paris Noisy Le Grand France

ISBN: (纸本)9781665497473

This paper applies Approximate computing (AC) techniques to the main elements which form a DNN hardware accelerator, namely, computation, communication, and memory subsystems. Specifically, approximate multipliers for computation, link voltage swing reduction for communication, voltage over-scaling for the internal SRAM memory, and lossy compression of the external DRAM memory are considered. The different AC techniques are applied in isolation as well as in conjunction with each other. A set of representative CNN models are mapped onto the approximated hardware accelerators and the trade-offs performance vs. energy vs. accuracy are derived for the execution of CNN inferences.

关键词： distributed processing Conferences Computational modeling Approximate computing Random access memory Voltage Hardware acceleration

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Coarse-Grained Floorplanning for streaming CNN applications on Multi-Die FPGAs 21

Coarse-Grained Floorplanning for streaming CNN applications ...

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21st IEEE international symposium on parallel and distributed computing (ISPDC)

作者： Kwadjo, Danielle Tchuinkou Tchinda, Erman Nghonda Bobda, Christophe Univ Florida ECE Dept Gainesville FL 32611 USA

ISBN: (数字)9781665488020

ISBN: (纸本)9781665488020

With the vast adoption of FPGAs in the cloud, it becomes necessary to investigate architectures and mechanisms for the efficient deployment of CNN into multi-FPGAs cloud Infrastructure. However, neural networks' growing size and complexity, coupled with communication and off-chip memory bottlenecks, make it increasingly difficult for multi-FPGA designs to achieve high resource utilization. In this work, we introduce a scalable framework that supports the efficient integration of CNN applications into a cloud infrastructure that exposes multi-Die FPGAs to cloud developers. Our framework is equipped is with two mechanisms to facilitate the deployment of CNN inference on FPGA. First, we propose a model to find the parameters that maximize the parallelism within the resource budget while maintaining a balanced rate between the layers. Then, we propose an efficient Coarse-Grained graph partitioning algorithm for high-quality and scalable routabffity-drive placement of CNN's components on the FPGAs. Prototyping results achieve an overall 37% higher frequency, with lower resource usage compared to a baseline implementation on the same number of FPGAs.

关键词： CNN acceleration FPGAs distributed inference FINN

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FHNTT: A flexible Number Theoretic Transform design based on hybrid-radix butterfly 22

FHNTT: A flexible Number Theoretic Transform design based on...

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22nd IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2024

作者： Li, Li Li, Rengang Zhao, Yaqian Li, Ruyang Su, Zhiyuan Li, Xuelei Ieit Systems Co. Ltd Jinan China Electronic Information Industry Co. Ltd Beijing China

ISBN: (纸本)9798331509712

Emerging technologies, such as cloud computing and artificial intelligence, significantly arouse concern about data security and privacy. Homomorphic encryption (HE) is a promising invention, which enables computation on encrypted data without decrypting it so as to ensure data security and privacy. Nevertheless, computation within homomorphic encryption involves time-consuming operations, e.g., Number Theoretic Transform (NTT). The tremendous computation overhead is the critical obstacle in deploying HE applications widely. Besides, in order to meet the performance and security requirements of different applications, it is pivotal to design parametric NTT architecture. In this paper, we propose a flexible and parametric NTT accelerating scheme based on hybrid-radix butterfly, named FHNTT. Specifically, we construct high radix butterfly units and divide the computation of them into several stages such that every stage can be performed pipelined. The number of required twiddle factors declines with the increase of radix value. In addition, we adopt address offset strategy to reduce memory consumption. We implement FHNTT on FPGA due to its fine-grained parallel computing capabilities and customized architecture. Empirical results show that FHNTT has an improved performance compared with other NTT architectures and supports a wide range of parameters. Concretely, FHNTT achieves up to 1.99 × to 2.78 × improvement in latency over other FPGA implementations and the memory utilization rate is up to 94%. Moreover, the flexibility makes FHNTT applicable to multiple use cases. © 2024 IEEE.

关键词： FPGA Acceleration Number Theoretic Transform parallel computing Parametric architecture

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An Analysis of Mapping Polybench Kernels to HPC CGRAs 36

An Analysis of Mapping Polybench Kernels to HPC CGRAs

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36th IEEE international parallel and distributed Processing symposium (IEEE IPDPS)

作者： Weinhardt, Markus Osnabruck Univ Appl Sci Fac Engn & Comp Sci Osnabruck Germany

ISBN: (纸本)9781665497473

This paper presents a detailed analysis of Mapping the Polybench C 4.2.1 kernels to Coarse-Grain Reconfigurable Arrays (CGRAs), targeting High-Performance computing (HPC). The results show that the Polybench kernels are well suited for acceleration on a CGRA due to their regular array accesses. However, seperately mapping the innermost loops of the Polybench kernels to a CGRA yields only limited speedups because the small size of the generated dataflow graphs limits the available parallelism and results in a low computational intensity. Therefore, loop transformations which will increase the parallelism and the speedups are suggested. While this work focuses on a specific CGRA and its compiler, the observations and conclusions are also transferable to other CGRAs and their compilers.

关键词： Coarse-Grained Reconfigurable Array High-Performance computing Polybench

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Litener: An Accelerator-Enabled Lightweight Container for Edge computing 36

Litener: An Accelerator-Enabled Lightweight Container for Ed...

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36th IEEE international parallel and distributed Processing symposium (IEEE IPDPS)

作者： Dyson, Ryan Reano, Carlos Queens Univ Belfast Belfast Antrim North Ireland Univ Valencia Valencia Spain

ISBN: (纸本)9781665497473

Containers supporting accelerators, such as Docker, include management tasks that require a significant amount of computing resources. While these resources are available in the Cloud, in other scenarios such as the Edge resources are more limited. An accelerator-enabled lightweight container would be desirable in such scenarios. In this paper, we analyse platforms to containerise applications using accelerators, including but not limited to Docker. After this analysis, we present a lightweight container, referred to as Litener, focused on using accelerators in scenarios with limited resources. Although the focus is on accelerators, many of the optimisations described can also be applied to scenarios that do not use accelerators. Experiments show a speedup of up to 7.78X when compared to other platforms.

关键词： Accelerator Container Edge Cloud

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FLEXLOG: A Shared Log for Stateful Serverless computing 23

FLEXLOG: A Shared Log for Stateful Serverless Computing

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32nd international symposium on High-Performance parallel and distributed computing (HPDC) part of the ACM Federated computing Research Conference (FCRC)

作者： Giantsidi, Dimitra Giortamis, Emmanouil Tornow, Nathaniel Dinu, Florin Bhatotia, Pramod Univ Edinburgh Edinburgh Midlothian Scotland Tech Univ Munich Munich Germany Huawei Munich Res Ctr Munich Germany

ISBN: (纸本)9798400701559

Stateful serverless applications need to persist their state and data. The existing approach is to store the data in general purpose storage systems. However, these approaches are not designed to meet the demands of serverless applications in terms of consistency, fault tolerance and performance. We present FlexLog, a storage system, specifically a distributed sharedlog, distinctively designedtomeet the requirements of stateful serverless computing while mitigating the relevant system bottlenecks. FlexLog's data layer leverages the state-of-the-art persistent memory (PM) to offer low latency I/O and improve performance. To match the performance, FlexLog's ordering layer employs a scalable design, namely a tree-structure set of sequencer nodes. Importantly, this design provides serverless applications with the flexibility to implement different consistency guarantees and to seamlessly support multi-tenancy configurations. We implement FlexLog from the ground up on a real hardware testbed and we also prove the correctness of our protocols. In particular, we evaluate FlexLog on a cluster of 6 machines with 800 GB Intel Optane DC PM over a 10 Gbps interconnect. Our evaluation shows that FlexLog scales to millions of operations per second while maintaining minimal latency. Our comparison with the state-of-the-art shared log for serverless, Boki, shows that we achieve 10x better throughput in the storage layer and 2x-4x lower latency in the ordering layer, while also providing flexibility to support different consistency properties and multi-tenancy.

关键词： Serverless computing Shared distributed Log Persistent Memory

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HAM-SpMSpV: an Optimized parallel Algorithm for Masked Sparse Matrix-Sparse Vector Multiplications on multi-core CPUs 24

HAM-SpMSpV: an Optimized Parallel Algorithm for Masked Spars...

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33rd international symposium on High-Performance parallel and distributed computing (HPDC)

作者： Xu, Lei Jia, Haipeng Zhang, Yunquan Wang, Luhan Jiang, Xianmeng Univ Chinese Acad Sci Chinese Acad Sci Inst Comp Technol Sch Comp Sci & Technol Beijing Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China

ISBN: (纸本)9798400704130

The efficiency of Sparse Matrix-Sparse Vector Multiplication (SpM-SpV) is critically important in fields such as machine learning and graph analytics. In certain algorithms, masked SpMSpV computes only a subset of the result entries. Despite its significance, this selective computation poses unique challenges, and existing algorithms often struggle to exploit the sparsity of the input and the mask vectors concurrently. To boost the efficiency of masked SpMSpV on shared memory architectures, we introduce a hybrid adaptive masked SpMSpV algorithm (HAM-SpMSpV) designed to select the efficient kernel automatically based on input features. This approach builds upon the foundation of a conventional algorithm, incorporating two novel masked SpMSpVs: the pre-bucketing masked SPA-based algorithm and the pre-masking bucketed hash-based algorithm. The newly proposed algorithms significantly expedite computation, especially in scenarios with high sparsity in input vectors and masks. Our evaluation involved extensive testing across a diverse range of real-world graphs, utilizing various sparsity of input vectors and masks. This rigorous testing confirmed that our approach notably outperforms existing solutions. Specifically, it achieves a speedup of up to 1.96 times compared to SuiteSparse:GraphBLAS and a remarkable 6.28 times relative to MKL Graph, demonstrating significant advancements in SpMSpV efficiency.

关键词： Sparse Matrix-Sparse Vector Multiplication (SpMSpV) Mask Shared Memory Adaptive Method

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