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Classification of Massively parallel Computer Architectures

Classification of Massively Parallel Computer Architectures

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Shami, Muhammad Ali Hemani, Ahmed Royal Inst Technol Dept ES S-16440 Stockholm Sweden

ISBN: (纸本)9780769546766

Faced with slowing performance and energy benefits of technology scaling, VLSI/Computer architectures have turned from parallel to massively parallel machines for personal and embedded applications in the form of multi and many core architectures. Additionally, in the pursuit of finding the sweet spot between engineering and computational efficiency, massively parallel Coarse Grain Reconfigurable Architectures(CRGAs) have been researched. While these articles have been surveyed, they have not been rigorously classified to enable objective differentiation and comparison for performance, area and flexibility. In this paper, we extend the well known Skillicorn taxonomy to create new classes, present a scoring system to rate these classes on flexibility, and present equations for early estimation of area and configuration overheads. Furthermore, we use this extended classification scheme to classify and compare 25 different massively parallel architectures that covers most of the reported CGRAs and other well known multi and many core architectures.

关键词： ARCHITECTURE scoring system MASSIVELY-parallel COMPUTERS Application Document embedded application core construction New classes classification scheme

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parallel Simulated Annealing for Fragment Based Sequence Alignment

Parallel Simulated Annealing for Fragment Based Sequence Ali...

引用

26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Correa, Jan Mendonca Magalhaes Alves de Melo, Alba Cristina Jacobi, Ricardo P. Boukerche, Azzedine Univ Brasilia Dept Comp Sci Brasilia DF Brazil Univ Ottawa SITE Ottawa ON K1N 6N5 Canada Kuwait Univ Safat 13060 Kuwait

ISBN: (纸本)9780769546766

Finding a biologically relevant sequence alignment may be difficult since several sequence alignments are possible, taking different parameters in consideration. A perceptron neuron can be used to associate weights to a set of alignment characteristics and then deciding if two residues should be aligned. Finding a good set of weights can be a hard problem and simulated annealing can be used to find a good set but can take a long time. In this paper, we propose a parallelization strategy for simulated annealing optimizing a Fragment Based Alignment in Linear Space (FBALS). The results were superior to the competing algorithm and the obtained speedups were compatible with the number of processing cores, indicating a good parallel strategy.

关键词： Sequence Alignment Linear Space Algorithms Simulated Annealing Perceptron

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Fixed-Priority Multiprocessor Scheduling: Critical Instant, Response Time and Utilization Bound

Fixed-Priority Multiprocessor Scheduling: Critical Instant, ...

引用

26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Guan, Nan Yi, Wang Uppsala Univ Uppsala Sweden

ISBN: (纸本)9780769546766

The rapid development of multi-core processors leads to a constantly increasing trend of deploying real-time systems on multi-core platforms, to satisfy the dramatically increasing high-performance and low-power requirements. This trend demands effective and efficient multiprocessor real-time scheduling techniques. The uniprocessor scheduling problem has been well studied during the last 40 years. However the multiprocessor scheduling problem to map tasks onto parallel architectures is a much harder challenge. In this work, we study several fundamental problems in multiprocessor scheduling, namely the critical instant, bounded responsiveness, and utilization bound.

关键词： Fixed-Priority Multiprocessor Scheduling Critical Instant Utilization Bound scheduling of multiprocessor Multi-core processors parallel architectures Fixed Priority instant Reaction Time Religious Missions power requirement Bound HIGH-PERFORMANCE

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A Highly parallel Reuse Distance Analysis Algorithm on GPUs

A Highly Parallel Reuse Distance Analysis Algorithm on GPUs

引用

26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Cui, Huimin Yi, Qing Xue, Jingling Wang, Lei Yang, Yang Feng, Xiaobing Chinese Acad Sci SKL Comp Architecture Inst Comp Technol Beijing Peoples R China Univ Texas CAS Dept Comp Sci San Antonio TX USA Univ New South Wales Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9780769546759

Reuse distance analysis is a runtime approach that has been widely used to accurately model the memory system behavior of applications. However, traditional reuse distance analysis algorithms use tree-based data structures and are hard to parallelize, missing the tremendous computing power of modern architectures such as the emerging GPUs. This paper presents a highly-parallel reuse distance analysis algorithm (HP-RDA) to speedup the process using the SPMD execution model of GPUs. In particular, we propose a hybrid data structure of hash table and local arrays to flatten the traditional tree representation of memory access traces. Further, we use a probabilistic model to correct any loss of precision from a straightforward parallelization of the original sequential algorithm. Our experimental results show that using an NVIDIA GPU, our algorithm achieves a factor of 20 speedup over the traditional sequential algorithm with less than 1% loss in precision.

关键词： Reuse reuse modern architectures Data structures sequential algorithm Hash table Precision Probabilistic Model Runtime Speeding algorithms

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Making Learning parallel Processing Interesting

Making Learning Parallel Processing Interesting

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Liu, Jie Wu, Yanwei Marsaglia, John Western Oregon Univ Div Comp Sci Monmouth OR 97361 USA

ISBN: (纸本)9780769546766

The abundant availability of multi-core computers makes "parallel computers" a common place and teaching Computer Science students to be able to design and develop parallel algorithms an urgent task. Most students recognize the needs of developing skills in parallel programming. However, since their Computer Science related curriculum are mostly taught based on sequential computers, introducing a new way of analysis and solving problems can be difficult. Making students interested in the subject can have a pivotal effect in the learning outcomes. In this short paper, we show several approaches we have been using to excite our students about learning parallel processing at our Concurrent Systems class, where parallel processing and parallel programming are taught. Some approach include showing students algorithms with an appeared impossible high performance, showing them simple steps to achieve 100% CPU utilization on multi-core computers, combining sequential algorithms they learned in the past to create new parallel algorithms, and challenging them with implementing some rather complex parallel algorithms.

关键词： parallel processing multi core algorithms students' interests curriculum

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A FAULT TOLERANCE SCHEDULING ALGORITHM FOR parallel TERRAIN ANALYSIS

A FAULT TOLERANCE SCHEDULING ALGORITHM FOR PARALLEL TERRAIN ...

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11th international symposium on distributed computing and Applications to Business, Engineering and Science (DCABES)

作者： Song, Xiaodong Dou, Wanfeng Tang, Guoan Yang, Kun Qian, Kejian Nanjing Normal Univ Key Lab Virtual Geog Environm Minist Educ Nanjing Jiangsu Peoples R China Nanjing Normal Univ Sch Comp Sci & Technol Nanjing Peoples R China

ISBN: (纸本)9780769548180

In recent years, due to the increasing calculation demands for the massive spatial data analysis, the parallel computing based on high-performance computers has become an inevitable trend of Digital Terrain Analysis (DTA in short). A key problem is to design fault-tolerant software to enhance the stability and robustness of scientific application. This paper presents an approach of failure recovery solution in distributed parallel computing environment. This approach to schedule the failing task is built by dividing all the failing data into several partitions according the calculating scale of failure. By means of the Fault-Tolerant Granularity Model, the scheduling algorithm can assign the failing task dynamically. Finally, two experiments focusing data size and failure size are discussed.

关键词： DEM Digital Terrain Analysis parallel computing Fault Tolerance

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The Spanish parallel Programming Contests and its use as an educational resource

The Spanish Parallel Programming Contests and its use as an ...

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Almeida, Francisco Cuenca, Javier Fernandez-Pascual, Ricardo Gimenez, Domingo Palomino Benito, Juan Alejandro Univ La Laguna Dept Estadist Invest Operat & Computac E-38207 San Cristobal la Laguna Spain Univ Murcia Dept Ingenieria & Tecnol Comp E-30001 Murcia Spain Univ Murcia Dept Informat & Sistemas E-30001 Murcia Spain Fundac Parque Cientifico Ctr Supercomputac Murcia Spain

ISBN: (纸本)9780769546766

The first Spanish parallel Programming Contest was organized in September 2011 within the Spanish Jornadas de Paralelismo. The aim of the contest is to disseminate parallelism among Computer Science students. The website and the material generated can be used for educational purposes. This paper comments on the organization of the contest and summarizes some training activities in which the material of the contest is being or can be used.

关键词： Programming contests Online judge parallel programming parallel algorithms

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Research on parallel computing algorithm of the second harmonic generation coefficients of nonlinear optical crystals based on MPI

Research on parallel computing algorithm of the second harmo...

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11th international symposium on distributed computing and Applications to Business, Engineering and Science (DCABES)

作者： Liu, Rong Zhang, Yongfan Wang, Meiqing Fuzhou Univ Coll Chem & Chem Engn Fuzhou 35000 Fujian Peoples R China Fuzhou Univ Coll Math & Comp Sci Fuzhou 35000 Fujian Peoples R China

ISBN: (纸本)9780769548180

The second harmonic generation (SHG) coefficients of nonlinear optical crystals play an important role in measuring the nonlinear optical properties of materials, but it is time-consuming to get the SHG coefficients by the theoretical calculation. In this paper, we proposed two sorts of parallel computing schemes for the SHG coefficients based on Message Passing Interface (MPI). If the amount of nodes is small, we will choose the the master slave model and statically allocated tasks;on the other hand, we will select the work pool mode for large amount of nodes, which can prevent the main node to suffer bottlenecks and get a sufficient load balancing. The experimental results show that with the master slave model, the efficiency reaches to 98% when using 4 nodes and declines with the nodes becoming large;while the work pool mode reaches the stable efficiency of 85% in the parallel computing with more than 24 processors.

关键词： Second Harmonic Generation Coefficient parallel computing Message Passing Interface (MPI)

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Modeling Power and Energy Usage of HPC Kernels

Modeling Power and Energy Usage of HPC Kernels

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Tiwari, Ananta Laurenzano, Michael A. Carrington, Laura Snavely, Allan San Diego Supercomp Ctr Performance Modeling & Characterizat Lab San Diego CA USA

ISBN: (纸本)9780769546766

Compute intensive kernels make up the majority of execution time in HPC applications. Therefore, many of the power draw and energy consumption traits of HPC applications can be characterized in terms of the power draw and energy consumption of these constituent kernels. Given that power and energy-related constraints have emerged as major design impediments for exascale systems, it is crucial to develop a greater understanding of how kernels behave in terms of power/energy when subjected to different compiler-based optimizations and different hardware settings. In this work, we develop CPU and DIMM power and energy models for three extensively utilized HPC kernels by training artificial neural networks. These networks are trained using empirical data gathered on the target architecture. The models utilize kernel-specific compiler-based optimization parameters and hardware tunables as inputs and make predictions for the power draw rate and energy consumption of system components. The resulting power draw and energy usage predictions have an absolute error rate that averages less than 5.5% for three important kernels - matrix multiplication (MM), stencil computation and LU factorization.

关键词： energy use Energy sources High Performance computing energy consumption Parameter optimization powered models execution time empirical data

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Deriving a Methodology for Code Deployment on Multi-Core Platforms via Iterative Manual Optimizations

Deriving a Methodology for Code Deployment on Multi-Core Pla...

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： McCool, Stuart Milligan, Peter Sage, Paul Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast Antrim North Ireland

ISBN: (纸本)9780769546766

In recent years, there has been what can only be described as an explosion in the types of processing devices one can expect to find within a given computer system. These include the multi-core CPU, the General Purpose Graphics Processing Unit (GPGPU) and the Accelerated Processing Unit (APU), to name but a few. The widespread uptake of these systems presents would-be users with at least two problems. Firstly, each device exposes a complex underlying architecture which must be appreciated in order to attain optimal performance. This is coupled with the fact that a single system can support an arbitrary number of such devices. Consequently, fully leveraging the performance capabilities of such a system must come at a cost - increasingly prolonged development times. Adhering to a methodology will have the significant industrial impact of reducing these development times. This paper describes the continued formulation of such a novel methodology. Two real world scientific programs are optimized for execution on the CUDA platform. Double precision accuracy and optimized speedups (which include PCI-E transfer times) of 15x and 17x are achieved.

关键词： heterogeneous computing GPGPU methodology toolset artificial intelligence characterization Racah Slater

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