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Using the Translation Lookaside Buffer to Map Threads in parallel Applications Based on Shared Memory

Using the Translation Lookaside Buffer to Map Threads in Par...

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Cruz, Eduardo H. M. Diener, Matthias Navaux, Philippe O. A. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9780769546759

The communication latency between the cores in multiprocessor architectures differs depending on the memory hierarchy and the interconnections. With the increase of the number of cores per chip and the number of threads per core, this difference between the communication latencies is increasing. Therefore, it is important to map the threads of parallel applications taking into account the communication between them. In parallel applications based on the shared memory paradigm, the communication is implicit and occurs through accesses to shared variables. For this reason, it is difficult to detect the communication pattern between the threads. Traditional approaches use simulation to monitor the memory accesses performed by the application, requiring modifications to the source code and drastically increasing the overhead. In this paper, we introduce a new light-weight mechanism to detect the communication pattern of threads using the Translation Lookaside Buffer (TLB). Our mechanism relies entirely on hardware features, which makes the thread mapping transparent to the programmer and allows it to be performed dynamically by the operating system. Moreover, no time consuming task, such as simulation, is required. We evaluated our mechanism with the NAS parallel Benchmarks (NPB) and achieved an accurate representation of the communication patterns. Using the detected communication patterns, we generated thread mappings using a heuristic method based on the Edmonds graph matching algorithm. Running the applications with these mappings resulted in performance improvements of up to 15.3%, reducing the number of cache misses by up to 31.1%.

关键词： Thread mapping parallel applications Shared memory TLB Translation Lookaside Buffer Interconnections Cache Misses

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Performance Study of SIMD Programming Models on Intel Multicore Processors

Performance Study of SIMD Programming Models on Intel Multic...

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Kristof, Peter Yu, Hongtao Li, Zhiyuan Tian, Xinmin Purdue Univ Dept Comp Sci W Lafayette IN 47906 USA Intel Corp Mobile Comp & Compilers Santa Clara CA USA

ISBN: (纸本)9780769546766

Modern multicore hardware employs a variety of parallel execution units, including multiple CPU cores for executing multiple threads simultaneously, vector units such as the Intel SIMD on the CPU cores, as well as GPU-like processing arrays. Availability of such unprecedented level of parallelism on main-stream computers offers an enormous potential to enable a new generation of computation-intensive nontraditional applications. On the other hand, how to best harness the hardware parallelism presents a new challenge to application programmers, language designers and compiler developers. In this paper, we evaluate the impact of several different parallel execution models, especially the new SIMD vectorization methods, supported by the latest Intel ICC compiler (version 12.1), using three computation-intensive nontraditional parallel applications as the test workload. Unlike traditional numerical programs, these applications use highly irregular data structures and therefore present nontrivial challenges to effective use of SIMD vector units. The first application is a game engine architecture requiring real-time performance. The second application involves a kd-tree traversal, which is typical to the state-of-the-art 3D ray-tracing applications. The last application processes data for large-scale weather visualization system in the order of tens of minutes. We compare the execution time of these codes using different SIMD models supported by ICC in conjunction with parallel threading under TBB and OpenMP.

关键词： Intel ICC compiler parallel programming SIMD optimization computer graphics

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An On-Demand Fast parallel Pseudo Random Number Generator with Applications

An On-Demand Fast Parallel Pseudo Random Number Generator wi...

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Banerjee, Dip Sankar Bahl, Aman Kumar Kothapalli, Kishore Int Inst Informat Technol Hyderabad 500032 Andhra Pradesh India

ISBN: (纸本)9780769546766

The use of manycore architectures and accelerators, such as GPUs, with good programmability has allowed them to be deployed for vital computational work. The ability to use randomness in computation is known to help in several situations. For such computations to be made possible on a general purpose computer, a source of randomness, or in general a pseudo random generator (PRNG), is essential. However, most of the PRNGs currently available on GPUs suffer from some basic drawbacks that we highlight in this paper. It is of high interest therefore to develop a parallel, quality PRNG that also works in an on demand model. In this paper we investigate a CPU+GPU hybrid technique to create an efficient PRNG. The basic technique we apply is that of random walks on expander graphs. Unlike existing generators available in the GPU programming environment, our generator can produce random numbers on demand as opposed to a one-time generation. Our approach produces 0.07 GNumbers per second. The quality of our generator is tested with industry standard tests. We also demonstrate two applications of our PRNG. We apply our PRNG to design a list ranking algorithm which demonstrates the on-demand nature of the algorithm and a Monte Carlo simulation which shows the high quality of our generator.

关键词： PRNG on-demand list ranking Monte Carlo GPGPU

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Sky computing platform for legacy distributed application

Sky computing platform for legacy distributed application

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2012 11th international symposium on parallel and distributed computing, ISPDC 2012

作者： Panica, Silviu Petcu, Dana Larrate, Iñigo Lazkanotegi Máhr, Tamás West University of Timisoara Research Institute e-Austria Timisoara Timisoara Romania Tecnalia Research and Innovation San Sebastian Spain AITIA International Inc. Budapest Hungary

ISBN: (纸本)9780769548050

The elasticity and scalability promised by the Cloud computing paradigm, intended mainly for the new Web 2.0 applications, attracts also legacy applications owners. The migration of legacy applications towards Cloud is a complex process and only few tools and platforms are available to assist the applications' owners in this process. This paper explains the challenges that arise in the migration process of legacy applications and also exposes the solution offered by an open-source platform as a service, named mOSAIC, designed to deal with applications portability between Clouds. © 2012 IEEE.

关键词： Platform as a Service (PaaS)

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Optimizing large-scale graph analysis on multithreaded, multicore platforms

Optimizing large-scale graph analysis on multithreaded, mult...

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Cong, Guojing Makarychev, Konstantin IBM Corp TJ Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)9780769546759

The erratic memory access pattern of graph algorithms makes it hard to optimize on cache-based architectures. While multithreading hides memory latency, it is unclear how hardware threads combined with caches impact the performance of typical graph workload. As modern architectures strike different balances between caching and multithreading, it remains an open question whether the benefit of optimizing locality behavior outweighs the cost. We study parallel graph algorithms on two different multi-threaded, multi-core platforms, that is, IBM Power7 and Sun Niagara2. Our experiments first demonstrate their performance advantage over prior architectures. We find nonetheless the number of hardware threads in either platform is not sufficient to fully mask memory latency. Our cache-friendly scheduling of memory accesses improves performance by up to 2.6 times on Power7 and prior cache-based architectures, yet the same technique significantly degrades performance on Niagara2. Software prefetching and manipulating the storage of the input to improve spatial locality improve performance by up to 2.1 times and 1.3 times on both platforms. Our study reveals interesting interplay between architecture and algorithm.

关键词： Multi-threading parallel Graph Algorithms Software Prefetch Traversal

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PARDA: A Fast parallel Reuse Distance Analysis Algorithm

PARDA: A Fast Parallel Reuse Distance Analysis Algorithm

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Niu, Qingpeng Dinan, James Lu, Qingda Sadayappan, P. Ohio State Univ Columbus OH 43210 USA Argonne Natl Lab Argonne IL 60439 USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9780769546759

Reuse distance is a well established approach to characterizing data cache locality based on the stack histogram model. This analysis so far has been restricted to offline use due to the high cost, often several orders of magnitude larger than the execution time of the analyzed code. This paper presents the first parallel algorithm to compute accurate reuse distances by analysis of memory address traces. The algorithm uses a tunable parameter that enables faster analysis when the maximum needed reuse distance is limited by a cache size upper bound. Experimental evaluation using the SPEC CPU 2006 benchmark suite shows that, using 64 processors and a cache bound of 8 MB, it is possible to perform reuse distance analysis with full accuracy within a factor of 13 to 50 times the original execution times of the benchmarks.

关键词： Data Locality Reuse Distance LRU Stack Distance Caching Performance Analysis

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Merge Path - parallel Merging Made Simple

Merge Path - Parallel Merging Made Simple

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Odeh, Saher Green, Oded Mwassi, Zahi Shmueli, Oz Birk, Yitzhak Technion Israel Inst Technol Dept Elect Engn IL-32000 Haifa Israel

ISBN: (纸本)9780769546766

Merging two sorted arrays is a prominent building block for sorting and other functions. Its efficient parallelization requires balancing the load among compute cores, minimizing the extra work brought about by parallelization, and minimizing inter-thread synchronization requirements. Efficient use of memory is also important. We present a novel approach to partitioning the two sorted arrays into pairs of contiguous sequences of elements, one from each array, such that 1) each pair comprises any desired total number of elements, and 2) the elements of each pair form a contiguous sequence in the final merged sorted array. While the resulting partition and the computational complexity are similar to those of certain previous algorithms, our approach is different, extremely intuitive, and offers interesting insights. Based on this, we present a synchronization-free, cache-efficient merging (and sorting) algorithm. While we use CREW PRAM as the basis, our algorithm is easily adaptable to additional architectures. In fact, our approach is even relevant to sequential cache-efficient sorting. The algorithms and performance results are presented, along with important cache-related insights.

关键词： component parallelism and concurrency parallel processors Sorting and searching

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The NiosII Dual-Core Processor Realizing the Digital Image Watermark

The NiosII Dual-Core Processor Realizing the Digital Image W...

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11th international symposium on distributed computing and Applications to Business, Engineering and Science (DCABES)

作者： He, Xinliang Li, Yuhui Li, Bo Zhu, Bowen Kunming Univ Sci & Technol Kunming Peoples R China

ISBN: (纸本)9780769548180

Digital watermark is the effective way to realize the copyright protection, the digital watermark application with the multi-core technology is being more and more widely in embedded systems today. This paper proposes a way that NiosII dual-core realizes the digital images embedding watermarking, including the DCT algorithm, NiosII dual-core parallel processing, barrier synchronization mechanism, realizing digital images embedding watermarking. The experiment results shows that dual-core is more efficient than single-core, images embedded with watermark comparing with the original one have no change in vision.

关键词： NiosII dual-core DCT parallel processing barrier synchronization

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Energy-aware scheduling: models and complexity results

Energy-aware scheduling: models and complexity results

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Aupy, Guillaume Ecole Normale Super Lyon LIP F-69364 Lyon 07 France

ISBN: (纸本)9780769546766

This paper presents several energy-aware scheduling algorithms whose design is optimized for different speed models. Dynamic Voltage and Frequency Scaling (DVFS) is a model frequently used to reduce the energy consumption of a schedule, but it has negative effect on reliability. While the reliability of a schedule can sometimes be neglected (battery powered systems such as cell-phones or personal computers), it becomes extremely important when considering massively parallel architectures (petascale, exascale). In this work, we consider the problem of minimizing the energy within a makespan constraint. Additionally, we consider two models, one that takes into account a reliability constraint, and one that does not. We assume that the mapping is given, say by an ordered list of tasks to execute on each processor, and we aim at optimizing the energy consumption while enforcing a prescribed bound on the execution time. While it is not possible to change the allocation of a task, it is possible to change its speed. Rather than using a local approach such as backfilling, we consider the problem as a whole and study the impact of several speed variation models on its complexity. To improve the reliability of a schedule while reducing the energy consumption, we allow for the re-execution of some tasks. We present several results in that framework, as well as future research plans.

关键词： energy consumption Variable speed ordered list Religious Missions execution time parallel architectures BACKFILL PROCESSOR

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Improving the Performance of Dynamical Simulations Via Multiple Right-Hand Sides

Improving the Performance of Dynamical Simulations Via Multi...

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26th IEEE international parallel and distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Liu, Xing Chow, Edmond Vaidyanathan, Karthikeyan Smelyanskiy, Mikhail Georgia Inst Technol Coll Comp Sch Computat Sci & Engn Atlanta GA 30332 USA Intel Corp Parallel Comp Lab Santa Clara CA 95054 USA

ISBN: (纸本)9780769546759

This paper presents an algorithmic approach for improving the performance of many types of stochastic dynamical simulations. The approach is to redesign existing algorithms that use sparse matrix-vector products (SPMV) with single vectors to instead use a more efficient kernel, the generalized SPMV (GSPMV), which computes with multiple vectors simultaneously. In this paper, we show how to redesign a dynamical simulation to exploit GSPMV in way that is not initially obvious because only one vector is available at a time. We study the performance of GSPMV as a function of the number of vectors, and demonstrate the use of GSPMV in the Stokesian dynamics method for the simulation of the motion of macromolecules in the cell. Specifically, for our application, we find that with modern multicore Intel microprocessors in clusters of up to 64 nodes, we can typically multiply by 8 to 16 vectors in only twice the time required to multiply by a single vector. After redesigning the Stokesian dynamics algorithm to exploit GSPMV, we measure a 30 percent speedup in performance in single-node, data parallel simulations.

关键词： sparse matrix-vector product (SPMV) iterative methods block Krylov subspace methods SIMD (SSE/AVX) Stokesian dynamics Brownian dynamics biological macromolecular simulation

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