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A Pipelining Approach to Informed Prefetching in distributed Multi-Level Storage Systems

A Pipelining Approach to Informed Prefetching in Distributed...

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11th IEEE international symposium on Network computing and Applications (NCA)

作者： Al Assaf, Maen M. Alghamdi, Mohammed I. Jiang, Xunfei Zhang, Ji QinO, Xiao Univ Jordan King Abdullah II Sch Informat Technol Amman Jordan Auburn Univ Dept Comp Sci & Software Engn Auburn AL 36849 USA Al Baha Univ Dept Comp Sci Al Baha Saudi Arabia

ISBN: (纸本)9780769547732

In this paper, we present an informed prefetching technique called IPODS that makes use of application-disclosed access patterns to prefetch hinted blocks in distributed multi-level storage systems. We develop a prefetching pipeline in IPODS, where an informed prefetching process is divided into a set of independent prefetching steps among multiple storage levels in a distributed system. In the IPODS system, while data blocks are prefetched from hard disks to memory buffers in remote storage servers, data blocks buffered in the servers are prefetched through networks to clients' local cache. We show that these two prefetching steps can be handled in a pipelining manner to improve I/O performance of distributed storage systems. Our IPODS technique differs itself from existing prefetching schemes in two ways. First, IPODS reduces applications' I/O stalls by keeping hinted data in clients' local caches and storage servers' fast buffers (e.g., solid state disks). Second, in a prefetching pipeline, multiple informed prefetching mechanisms semi-dependently coordinate to fetch blocks (1) from low-level (slow) to high-level (fast) storage devices in servers and (2) from high-level devices in servers to clients' local cache. The prefetching pipeline in IPODS judiciously hides network latencies in distributed storage systems, thereby reducing the overall I/O access time in distributed systems. Using a wide range of real-world I/O traces, our experiments show that IPODS can improve noticeably I/O performance of distributed storage systems.

关键词： Informed prefetching pipelining parallel storage systems distributed multi-level storage system

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Autonomic resource allocation in virtualized data centers

Autonomic resource allocation in virtualized data centers

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2012 10th IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2012

作者： Zhang, Wei Zhu, Mingfa Xiao, Limin Liu, Jiajun Wu, Qimeng Song, Ying Sun, Yuzhong Computer Science Beihang University Beijng China Institute of Computing Technology Beijing China

ISBN: (纸本)9780769547015

Virtualization has been widely adopted in data centers for improving efficiency and flexibility. Multiple applications are co-hosted in virtualized data centers. In order to meet the Service Level Agreements (SLA), how to allocate resources for multiple applications is an important and challenging task, especially when dealing with fluctuating workloads and complex server applications. Virtual Machine Monitor provides fine-grained resource allocation and live migration. In this paper, we develop RTCOIN-Qclouds, a response time-aware, cost-aware and interference-aware control framework that tunes resource allocation, which ensures a high level of meeting the SLAs. Every physical machine's resources are assigned to multiple virtual machines which run on it based on application's response time, rather than traditional methods based on resource utilization. Virtual machine migration allows data centers to rebalance workloads across physical machines. However, migration actions may lead to performance impact during the migration process. Current virtualization techniques do not provide effective performance isolation between virtual machines (VMs). Specially, hidden contention for physical resources impacts performance differently in different virtual machines. As to the problem of selecting which virtual machines to be migrated, we consider migration cost. As to the problem of selecting which physical machine to be placed, we consider performance interference. Furthermore, we experimentally validate the effectiveness of response time-aware resource allocation in our framework using microbenchmarks. © 2012 IEEE.

关键词： Virtual machine

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An analysis of provisioning and allocation policies for infrastructure-as-a-service clouds 12

An analysis of provisioning and allocation policies for infr...

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12th IEEE/ACM international symposium on Cluster, Cloud and Grid computing, CCGrid 2012

作者： Villegas, David Antoniou, Athanasios Sadjadi, Seyed Masoud Iosup, Alexandru School of Computing and Information Sciences Florida International University Miami FL United States Parallel and Distributed Systems Group Delft University of Technology Delft Netherlands

ISBN: (纸本)9780769546919

Today, many commercial and private cloud computing providers offer resources for leasing under the infrastructure as a service (IaaS) paradigm. Although an abundance of mechanisms already facilitate the lease and use of single infrastructure resources, to complete multi-job workloads IaaS users still need to select adequate provisioning and allocation policies to instantiate resources and map computational jobs to them. While such policies have been studied in the past, no experimental investigation in the context of clouds currently exists that considers them jointly. In this paper we present a comprehensive and empirical performance-cost analysis of provisioning and allocation policies in IaaS clouds. We first introduce a taxonomy of both types of policies, based on the type of information used in the decision process, and map to this taxonomy eight provisioning and four allocation policies. Then, we analyze the performance and cost of these policies through experimentation in three clouds, including Amazon EC2. We show that policies that dynamically provision and/or allocate resources can achieve better performance and cost. Finally, we also look at the interplay between provisioning and allocation, for which we show preliminary results. © 2012 IEEE.

关键词： Taxonomies

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The Myrmics Memory Allocator: Hierarchical, Message-Passing Allocation for Global Address Spaces 12

The Myrmics Memory Allocator: Hierarchical, Message-Passing ...

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2012 international symposium on Memory Management

作者： Lyberis, Spyros Pratikakis, Polyvios Nikolopoulos, Dimitrios S. Schulz, Martin Gamblin, Todd de Supinski, Bronis R. Lawrence Livermore Natl Lab CASC Livermore CA USA Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast BT7 1NN Antrim North Ireland

ISBN: (纸本)9781450313506

Constantly increasing hardware parallelism poses more and more challenges to programmers and language designers. One approach to harness the massive parallelism is to move to task-based programming models that rely on runtime systems for dependency analysis and scheduling. Such models generally benefit from the existence of a global address space. This paper presents the parallel memory allocator of the Myrmics runtime system, in which multiple allocator instances organized in a tree hierarchy cooperate to implement a global address space with dynamic region support on distributed memory machines. The Myrmics hierarchical memory allocator is step towards improved productivity and performance in parallel programming. Productivity is improved through the use of dynamic regions in a global address space, which provide a convenient shared memory abstraction for dynamic and irregular data structures. Performance is improved through scaling on many-core systems without system-wide cache coherency. We evaluate the stand-alone allocator on an MPI-based x86 cluster and find that it scales well for up to 512 worker cores, while it can outperform Unified parallel C by a factor of 3.7-10.7x.

关键词： parallel Memory Allocator GAS

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Empirical autotuning of two-level parallel linear algebra routines on large cc-NUMA systems

Empirical autotuning of two-level parallel linear algebra ro...

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2012 10th IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2012

作者： Cámara, Jesus Cuenca, Javier Giménez, Domingo Vidal, Antonio M. Department of Informatic and Systems University of Murcia 30071 Murcia Spain Department of Engineere and Technology of Computers University of Murcia 30071 Murcia Spain Department of Informatic Systems and Computing Polytechnic University of Valencia 46022 Valencia Spain

ISBN: (纸本)9780769547015

In large cc-NUMA systems the efficient use of the different levels of the memory hierarchy is not an easy task, and the performance of multithreading implementations of the libraries decreases when the number of cores used increases, so producing an important lost of efficiency. To alleviate this problem, routines with multilevel parallelism can be developed by combining OpenMP and BLAS parallelism. In that way, higher performance can be achieved, but it is necessary to develop some autotuning technique for the appropriate selection of the number of threads to use at each level. The selection can be made through theoretical models of the execution time or some installation methodology. This work analyses some installation techniques for a two-level matrix multiplication routine, with the aim of developing a valid methodology for other linear algebra routines in large cc-NUMA systems. The basic ideas of the two-level parallelisation and the installation methodology are discussed and some experimental results are commented on. © 2012 IEEE.

关键词： Linear algebra

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Multithreaded algorithms for maxmum matching in bipartite graphs

Multithreaded algorithms for maxmum matching in bipartite gr...

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2012 IEEE 26th international parallel and distributed Processing symposium, IPDPS 2012

作者： Azad, Ariful Halappanavar, Mahantesh Rajamanickam, Sivasankaran Boman, Erik G. Khan, Arif Pothen, Alex Purdue University United States Pacific Northwest National Laboratory United States Sandia National Laboratories United States

ISBN: (纸本)9780769546759

We design, implement, and evaluate algorithms for computing a matching of maximum cardinality in a bipartite graph on multicore and massively multithreaded computers. As computers with larger numbers of slower cores dominate the commodity processor market, the design of multithreaded algorithms to solve large matching problems becomes a necessity. Recent work on serial algorithms for the matching problem has shown that their performance is sensitive to the order in which the vertices are processed for matching. In a multithreaded environment, imposing a serial order in which vertices are considered for matching would lead to loss of concurrency and performance. But this raises the question: Would parallel matching algorithms on multithreaded machines improve performance over a serial algorithm? We answer this question in the affirmative. We report efficient multithreaded implementations of three classes of algorithms based on their manner of searching for augmenting paths: breadth-first-search, depth-first-search, and a combination of both. The Karp-Sipser initialization algorithm is used to make the parallel algorithms practical. We report extensive results and insights using three shared-memory platforms (a 48-core AMD Opteron, a 32-coreIntel Nehalem, and a 128-processor Cray XMT) on a representative set of real-world and synthetic graphs. To the best of our knowledge, this is the first study of augmentation-based parallel algorithms for bipartite cardinality matching that demonstrates good speedups on multithreaded shared memory multiprocessors. © 2012 IEEE.

关键词： parallel algorithms

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Research of context situation awareness technology

Research of context situation awareness technology

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作者： Shi, Dianxi Wu, Zhendong Ding, Bo Yan, Huining National Key Laboratory for Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769546698

Context situation, which means a snapshot of the status of the real world, is formed by integrating a large amount of contexts collected from various resources. How to get the context situation and use the situation to provide better services is a challenging issue. In this paper, we focused on this challenge on the basis of the mobile cloud computing architecture. An abstract model is proposed in this paper to uniformly collect the context and send them to cloud. A rule-based large-scale context aggregation algorithm is also proposed which utilizes the MapReduce computing paradigm. Finally, a large-scale context management framework based on the abstract model and the context aggregation algorithm is proposed, and a real-time traffic demo is implemented to verify the validity of the framework. © 2012 IEEE.

关键词： MapReduce

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Compiling C/C++ SIMD extensions for function and loop vectorizaion on multicore-SIMD processors

Compiling C/C++ SIMD extensions for function and loop vector...

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2012 IEEE 26th international parallel and distributed Processing symposium Workshops, IPDPSW 2012

作者： Tian, Xinmin Saito, Hideki Girkar, Milind Preis, Serguei V. Kozhukhov, Sergey S. Cherkasov, Aleksei G. Nelson, Clark Panchenko, Nikolay Geva, Robert Mobile Computing and Compilers Software and Service Group Intel Corporation Santa Clara CA United States

ISBN: (纸本)9780769546766

SIMD vectorization has received significant attention in the past decade as an important method to accelerate scientific applications, media and embedded applications on SIMD architectures such as Intel® SSE, AVX, and IBM* AltiVec. However, most of the focus has been directed at loops, effectively executing their iterations on multiple SIMD lanes concurrently relying upon program hints and compiler analysis. This paper presents a set of new C/C++ high-level vector extensions for SIMD programming, and the Intel® C++ product compiler that is extended to translate these vector extensions and produce optimized SIMD instruction sequences of vectorized functions and loops. For a function, our main idea is to vectorize the entire function for callers instead of just vectorizing loops (if any) inside the function. It poses the challenge of dealing with complicated control-flow in the function body, and matching caller and callee for SIMD vector calls while vectorizing caller functions (or loops) and callee functions. Our compilation methods for automatically compiling vector extensions are described. We present performance results of several non-trivial visual computing, computational, and simulation workloads, utilizing SIMD units through the vector extensions on Intel® Multicore 128-bit SIMD processors, and we show that significant SIMD speedups (3.07x to 4.69x) are achieved over the serial execution. © 2012 IEEE.

关键词： Vectors

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Design of peer-to-peer traffic classification system model based on cloud computing

Design of peer-to-peer traffic classification system model b...

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2012 international Applied Mechanics, Mechatronics Automation symposium, IAMMAS 2012

作者： Liu, XiZi Xu, YaBin Beijing Information Science and Technology University Beijing China

ISBN: (纸本)9783037854266

The advantages and disadvantages of mainstream peer-to-peer (P2P) traffic classification technology in the current application are analyzed. As existing traffic classification tools fail to meet the super flow, as well as continuous increasing of network bandwidth, a cloud-based P2P traffic classification system model is proposed, which use the distributed parallel computing architecture named MapReduce based on hadoop. © (2012) Trans Tech Publications, Switzerland.

关键词： MapReduce

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Fast sparse matrix matrix product based on ELLR-T and GPU computing

Fast sparse matrix matrix product based on ELLR-T and GPU co...

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2012 10th IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2012

作者： Vázquez, F. Ortega, G. Fernández, J.J. Garcia, I. Garzon, E.M. Ctra. Sacramento s/n 04120 Almería Spain Campus UAM Darwin 3 Cantoblanco 28049 Madrid Spain Dpt. of Comput. Archit. Univ. of Málaga 29071 Málaga Spain

ISBN: (纸本)9780769547015

A wide range of applications in engineering and scientific computing are based on the computation of matrices products, where one of them is sparse. The computational requirements of these operations are very high when dimensions of the matrices increase. The goal of this work is the acceleration of the sparse matrix matrix product (SpMM) on Graphics Processing Units (GPUs). The operation SpMM can be computed by a set of sparse matrix vector operations (SpMV). However, this approach does not reach optimal performance because it cannot benefit from the large value of the ratio computation/memory access associated to the SpMM operation. In this work a routine called FastSpMM is described and its performance evaluated. FastSpMM can be considered as an extension of the ELLRT routine to compute SpMV on GPUs which is based on the ELLPACK-R storage format for sparse matrices. FastSpMM combines the high ratio computation/memory access with the advantages of ELLR-T to exploit the GPU architecture. The CUSPARSE library, supplied by NVIDIA, which also includes routines to compute SpMM on GPUs is used in this work as a reference for performance comparison. Experimental evaluations based on a representative set of test matrices show that FastSpMM outperforms the corresponding CUSPARSE routine in terms of performance. © 2012 IEEE.

关键词： Graphics processing unit

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