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The Myrmics Memory Allocator: Hierarchical, Message-Passing Allocation for Global Address Spaces 12

The Myrmics Memory Allocator: Hierarchical, Message-Passing ...

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2012 international symposium on Memory Management

作者： Lyberis, Spyros Pratikakis, Polyvios Nikolopoulos, Dimitrios S. Schulz, Martin Gamblin, Todd de Supinski, Bronis R. Lawrence Livermore Natl Lab CASC Livermore CA USA Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast BT7 1NN Antrim North Ireland

ISBN: (纸本)9781450313506

Constantly increasing hardware parallelism poses more and more challenges to programmers and language designers. One approach to harness the massive parallelism is to move to task-based programming models that rely on runtime systems for dependency analysis and scheduling. Such models generally benefit from the existence of a global address space. This paper presents the parallel memory allocator of the Myrmics runtime system, in which multiple allocator instances organized in a tree hierarchy cooperate to implement a global address space with dynamic region support on distributed memory machines. The Myrmics hierarchical memory allocator is step towards improved productivity and performance in parallel programming. Productivity is improved through the use of dynamic regions in a global address space, which provide a convenient shared memory abstraction for dynamic and irregular data structures. Performance is improved through scaling on many-core systems without system-wide cache coherency. We evaluate the stand-alone allocator on an MPI-based x86 cluster and find that it scales well for up to 512 worker cores, while it can outperform Unified parallel C by a factor of 3.7-10.7x.

关键词： parallel Memory Allocator GAS

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Fast sparse matrix matrix product based on ELLR-T and GPU computing

Fast sparse matrix matrix product based on ELLR-T and GPU co...

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2012 10th IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2012

作者： Vázquez, F. Ortega, G. Fernández, J.J. Garcia, I. Garzon, E.M. Ctra. Sacramento s/n 04120 Almería Spain Campus UAM Darwin 3 Cantoblanco 28049 Madrid Spain Dpt. of Comput. Archit. Univ. of Málaga 29071 Málaga Spain

ISBN: (纸本)9780769547015

A wide range of applications in engineering and scientific computing are based on the computation of matrices products, where one of them is sparse. The computational requirements of these operations are very high when dimensions of the matrices increase. The goal of this work is the acceleration of the sparse matrix matrix product (SpMM) on Graphics Processing Units (GPUs). The operation SpMM can be computed by a set of sparse matrix vector operations (SpMV). However, this approach does not reach optimal performance because it cannot benefit from the large value of the ratio computation/memory access associated to the SpMM operation. In this work a routine called FastSpMM is described and its performance evaluated. FastSpMM can be considered as an extension of the ELLRT routine to compute SpMV on GPUs which is based on the ELLPACK-R storage format for sparse matrices. FastSpMM combines the high ratio computation/memory access with the advantages of ELLR-T to exploit the GPU architecture. The CUSPARSE library, supplied by NVIDIA, which also includes routines to compute SpMM on GPUs is used in this work as a reference for performance comparison. Experimental evaluations based on a representative set of test matrices show that FastSpMM outperforms the corresponding CUSPARSE routine in terms of performance. © 2012 IEEE.

关键词： Graphics processing unit

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Proceedings - 24th international symposium on Computer Architecture and High Performance computing, SBAC-PAD 2012

Proceedings - 24th International Symposium on Computer Archi...

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24th international symposium on Computer Architecture and High Performance computing, SBAC-PAD 2012

The proceedings contain 36 papers. The topics discussed include: the network adapter: the missing link between MPI applications and network performance;on the efficiency of register file versus broadcast interconnect for collective communications in data-parallel hardware accelerators;network endpoints for clusters of SMPs;assessing energy efficiency of fault tolerance protocols for HPC systems;using heterogeneous networks to improve energy efficiency in direct coherence protocols for many-core CMPs;energy savings via dead sub-block prediction;scalable thread scheduling in asymmetric multicores for power efficiency;divergence analysis with affine constraints;exploiting concurrent GPU operations for efficient work stealing on multi-GPUs;sparse fast Fourier transform on GPUs and multi-core CPUs;cloud workload analysis with SWAT;and scalable algorithms for distributed-memory adaptive mesh refinement.

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Social aspects for opportunistic communication

Social aspects for opportunistic communication

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2012 11th international symposium on parallel and distributed computing, ISPDC 2012

作者： Ciobanu, Radu Ioan Dobre, Ciprian Cristea, Valentin Al-Jumeily, Dhiya University Politehnica of Bucharest Faculty of Automatic Control and Computers Bucharest Romania School of Computing and Mathematical Sciences Liverpool John Moores University Liverpool United Kingdom

ISBN: (纸本)9780769548050

As wireless and 3G networks become more crowded, users with mobile devices experience difficulties in accessing the network. Opportunistic networks, created between mobile phones using local peer-to-peer connections, have the potential to solve such problems by dispersing some of the traffic to neighbouring smart phones. Recently various opportunistic routing and dissemination algorithms were proposed and evaluated in various scenarios emulating real-world phenomena as close as possible. Such algorithms generally rely on mobility patterns of users and the context of communication. In this we investigate the addition of social data to improve the performance of communication algorithms and data transmission schema. When the routing decision is influenced by the chance of a particular user being able to successfully carry the data to the next hop, we believe that opportunistic communication algorithms could greatly benefit not only from learning the behaviour of users, but also their history of contacts coupled with the online social familiarity patterns between them. We believe users tend to be in contact more with familiar sets of users, with whom they share common interests. We investigate our approach using two real-world traces collected in two different environments. We first investigate our hypothesis using mobility data collected in an indoor academic environment. We then evaluate our assumptions in an outdoor urban scenario. We present an analysis of our findings, highlighting key social and mobility behaviour factors that can influence such opportunistic solutions. Most importantly, we show that by adding knowledge such as social links between participants in an opportunistic network routing and dissemination algorithms can be greatly improved. © 2012 IEEE.

关键词： Smartphones

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Multilevel SLA-based QoS support in grids

Multilevel SLA-based QoS support in grids

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2012 10th IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2012

作者： Conejero, Javier Tomás, Luis Caminero, Blanca Carrión, Carmen Dept. of Computing Systems University of Castilla-La Mancha Albacete Spain

ISBN: (纸本)9780769547015

The need of mechanisms to guarantee the Quality of Service (QoS) in Grid environments has empowered the interest on Service Level Agreements (SLAs), which represent the contract established by negotiation between users and service providers that must be accomplished. Consequently, the SLAs contain numerous terms related to the QoS expected. The aim of this paper is to address different QoS levels in Grid environments by using specific metrics on SLAs. These metrics represent the expected QoS by the user for the given service level terms. Hence, a characterization and classification of these terms, making a differentiation of QoS in levels, is needed in order to improve the number of fulfilled agreements. Our proposal is based on a WS-Agreement compliant architecture developed to provide support for SLAs in Grid environments, also providing a framework prepared for new terms and policy definitions. More precisely, the QoS expected by users is clearly defined in three levels. These levels are used to classify the compromise adquired by each SLA (depending on the expectations of the user that submitted it) and deal with the confidence that Grid resources provide. The evaluation on a real Grid testbed shows the efficiency of the proposal. © 2012 IEEE.

关键词： Quality of service

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Techniques for Mapping Synthetic Aperture Radar Processing Algorithms to Multi-GPU Clusters

Techniques for Mapping Synthetic Aperture Radar Processing A...

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12th IEEE international symposium on Signal Processing and Information Technology (ISSPIT)

作者： Hayden, Eric Schmalz, Mark Chapman, William Ranka, Sanjay Sahni, Sartaj Seetharaman, Gunasekaran Univ Florida Dept CISE Gainesville FL 32611 USA Air Force Res Lab Griffiss AFB NY 13441 USA

ISBN: (纸本)9781467356046

This paper presents a design for parallel processing of synthetic aperture radar (SAR) data using multiple Graphics Processing Units (GPUs). Our approach supports real-time reconstruction of a two-dimensional image from a matrix of echo pulses and their response values. Key to runtime efficiency is a partitioning scheme that divides the output image into tiles and the input matrix into a collection of pulses associated with each tile. Each image tile and its associated pulse set are distributed to thread blocks across multiple GPUs, which support parallel computation with near-optimal I/O cost. The partial results are subsequently combined by a host CPU. Further efficiency is realized by the GPU's low-latency thread scheduling, which masks memory access latencies. Performance analysis quantifies runtime as a function of input/output parameters and number of GPUs. Experimental results were generated with 10 nVidia Tesla C2050 GPUs having maximum throughput of 972 Gflop/s. Our approach scales well for output (reconstructed) image sizes from 2,048 x 2,048 pixels to 8,192 x 8,192 pixels.

关键词： High performance computing Synthetic aperture radar Image reconstruction Graphics processing unit

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Towards Interactive Steering of a Very Large Floating Structure Code by Using HPC parallelisation Strategies

Towards Interactive Steering of a Very Large Floating Struct...

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14th international symposium on Symbolic and Numeric Algorithms for Scientific computing (SYNASC)

作者： Frisch, Jerome Gao, Ruiping Mundani, Ralf-Peter Wang, Chien Ming Rank, Ernst Tech Univ Munich Chair Computat Engn D-80290 Munich Germany Natl Univ Singapore Dept Civil & Environm Engn Singapore Singapore

ISBN: (纸本)9780769549347;9781467350266

Very large floating structures (VLFSs) have been used for broad applications such as floating storage facilities, floating piers, floating bridges, floating airports, entertainment facilities, even habitation, and other purposes [1]. Owing to its small bending rigidity, VLFS deforms elastically when subjected to wave action. This elastic deformation due to wave is called hydroelastic response and it can be obtained by solving the interaction between the surface wave and the floating structure in the frequency domain. In solving the fluid-structure interaction, the floating structure can be modelled by applying the finite element method, whereas the fluid part may be analyzed by using the Green's function method. When using the Green's function which satisfies the boundary condition on the free-surface, the sea bottom and that at infinite distance from the floating structure, the unknown parameters to be determined for the fluid part can be minimized to be only those associated with the wetted surface of the floating structure. However, in the evaluation of the Green's function, extensive computation time O(N-2) is needed (N is the number of unknowns). Therefore, acceleration techniques are necessary to tackle the computational complexity. Nowadays, standard multi-core office PCs are already quite powerful if all the cores can be used efficiently. This paper will show different parallelisation strategies for speeding up the Green's function computation. A shared memory based implementation as well as a distributed memory concept will be analysed regarding speed-up and efficiency. For large computations, batch jobs can be used to compute detailed results in high resolution on a large computational cluster or supercomputer. Different speed-up computations on clusters will be included for showing strong speed-up results.

关键词： parallel computation message passing paradigm shared memory concept hybrid parallelisation engineering application very large floating structure

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Automatic offloading C++ expression templates to CUDA enabled GPUs

Automatic offloading C++ expression templates to CUDA enable...

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2012 IEEE 26th international parallel and distributed Processing symposium Workshops, IPDPSW 2012

作者： Chen, Jie Joo, Balint Watson III, William Edwards, Robert Scientific Computing Group Jefferson Lab. Newport News VA 23606 United States Theory Center Jefferson Lab. Newport News VA 23606 United States

ISBN: (纸本)9780769546766

In the last few years, many scientific applications have been developed for powerful graphics processing units (GPUs) and have achieved remarkable speedups. This success can be partially attributed to high performance host callable GPU library routines that are offloaded to GPUs at runtime. These library routines are based on C/C++-like programming toolkits such as CUDA from NVIDIA and have the same calling signatures as their CPU counterparts. Recently, with the sufficient support of C++ templates from CUDA, the emergence of template libraries have enabled further advancement in code reusability and rapid software development for GPUs. However, Expression Templates (ET), which have been very popular for implementing data parallel scientific software for host CPUs because of their intuitive and mathematics-like syntax, have been underutilized by GPU development libraries. The lack of ET usage is caused by the difficulty of offloading expression templates from hosts to GPUs due to the inability to pass instantiated expressions to GPU kernels as well as the absence of the exact form of the expressions for the templates at the time of coding. This paper presents a general approach that enables automatic offloading of C++ expression templates to CUDA enabled GPUs by using the C++ metaprogramming technique and Just-In-Time (JIT) compilation methodology to generate and compile CUDA kernels for corresponding expression templates followed by executing the kernels with appropriate arguments. This approach allows developers to port applications to run on GPUs with virtually no code modifications. More specifically, this paper uses a large ET based data parallel physics library called QDP++ as an example to illustrate many aspects of the approach to offload expression templates automatically and to demonstrate very good speedups for typical QDP++ applications running on GPUs against running on CPUs using this method of offloading. In addition, this approach of automatic offloa

关键词： Graphics processing unit

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12th international symposium on Trends in Functional Programming, TFP 2011

12th International Symposium on Trends in Functional Program...

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12th international symposium on Trends in Functional Programming, TFP 2011

ISBN: (纸本)9783642320361

The proceedings contain 12 papers. The special focus in this conference is Trends in Functional Programming. The topics include: Constraint-free type error slicing;subtyping by folding an inductive relation into a coinductive one;a library for generating compilers;towards modular compilers for effects;a distributed computing library for objective caml;forming parallel Haskell programs using novel refactoring techniques;functional high performance financial it;thread-safe priority queues in Haskell based on skiplists;correctness proof and efficient implementation;from structural recursion to generative and accumulative recursion;a graphical language and tool for defining itask workflows;applicative shortcut fusion.

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Speculative symbolic execution

Speculative symbolic execution

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2012 IEEE 23rd international symposium on Software Reliability Engineering, ISSRE 2012

作者： Zhang, Yufeng Chen, Zhenbang Wang, Ji National Laboratory for Parallel and Distributed Processing Department of Computing Science National University of Defense Technology Changsha China

ISBN: (纸本)9780769548883

Symbolic execution is an effective path oriented and constraint based program analysis technique. Recently, there is a significant development in the research and application of symbolic execution. However, symbolic execution still suffers from the scalability problem in practice, especially when applied to large-scale or very complex programs. In this paper, we propose a new fashion of symbolic execution, named Speculative Symbolic Execution (SSE), to speed up symbolic execution by reducing the invocation times of constraint solver. In SSE, when encountering a branch statement, the search procedure may speculatively explore the branch without regard to the feasibility. Constraint solver is invoked only when the speculated branches are accumulated to a specified number. In addition, we present a key optimization technique that enhances SSE greatly. We have implemented SSE and the optimization technique on Symbolic Pathfinder (SPF). Experimental results on six programs show that, our method can reduce the invocation times of constraint solver by 20.7% to 48.7% (with an average of 29.9%), and save the search time from 23.6% to 43.6% (with an average of 30%). © 2012 IEEE.

关键词： Java programming language

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