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Improving High-Performance Sparse Libraries Using Compiler-Assisted Specialization: A PETSc Case Study

Improving High-Performance Sparse Libraries Using Compiler-A...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Shreyas Ramalingam Mary Hall Chun Chen School of Computing University of Utah USA

Scientific libraries are written in a general way in anticipation of a variety of use cases that reduce optimization opportunities. Significant performance gains can be achieved by specializing library code to its execution context: the application in which it is invoked, the input data set used, the architectural platform and its backend compiler. Such specialization is not typically done because it is time consuming, leads to nonportable code and requires performance-tuning expertise that application scientists may not have. Tool support for library specialization in the above context could potentially reduce the extensive understanding required while significantly improving performance, code reuse and portability. In this work, we study the performance gains achieved by specializing the single processor sparse linear algebra functions in PETSc (Portable, Extensible Toolkit for Scientific Computation) in the context of three scalable scientific applications on the Hopper Cray XE6 Supercomputer at NERSC. We use CHiLL (Compos able High-Level Loop Transformation Framework) to apply source level transformations tailored to the special needs of sparse computations and automatically generate highly optimized PETSc functions. We demonstrate significant performance improvements of more than 1.8X on the library functions and overall gains of 9 to 24% on three scalable applications that use PETSc's sparse matrix capabilities.

关键词： Sparse matrices Libraries Optimization Context Linear algebra Computer architecture Performance gain

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L2 Cache Performance Analysis and Optimizations for Processing HDF5 Data on Multi-core Nodes

L2 Cache Performance Analysis and Optimizations for Processi...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Rajdeep Bhowmik Madhusudhan Govindaraju Grid and Cloud Computing Research Laboratory Department of Computer Science SUNY at Binghamton Binghamton NY USA

It is important to design and develop scientific middleware libraries to harness the opportunities presented by emerging multi-core processors that are available on grid and cloud environments. Scientific middleware libraries not adhering or adapting to this programming paradigm can suffer from severe performance limitations while executing on emerging multi-core processors. In this paper, we focus on the utilization of a critical shared resource on chip multiprocessors (CMPs), the L2 cache. The way in which an application schedules and assigns processing work to each thread determines the access pattern of the shared L2 cache, which may result in either enhancing or diminishing the effects of memory latency on a multi-core processor. Therefore, while processing scientific datasets such as HDF5, it is essential to conduct fine-grained analysis of cache utilization, to make informed processing and scheduling decisions in multi-threaded programming. In this paper, using the TAU toolkit for performance feedback from dual- and quad-core machines, we analyze and recommend methods for effective scheduling of threads on multi-core nodes to augment the performance of scientific applications processing HDF5 data. We discuss the benefits that can be achieved by using L2 Cache-Affinity and L2 Balanced-Set based scheduling algorithms for improving L2 cache performance and effectively the overall execution time.

关键词： Instruction sets Multicore processing Optimization Processor scheduling Hardware Libraries Middleware

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Optimization Of parallel I/O For Cannon's algorithm Based On Lustre

Optimization Of Parallel I/O For Cannon's algorithm Based On...

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The Eleventh international symposium on distributed computing and Applications to Business,Engineering and Science(DCABES2012)(第十一届分布式计算及其应用国际学术研讨会)(原名:电子商务、工程及科学领域的分布式计算和应用国际学术研讨会)

作者： Yunchun Li Hongda Li Beijing Key laboratory of network technology Computer Science Department Beihang University Beijing China

Matrix multiplication is one of the most important operations in linear algebra,widely used in many fields of science and ***'s algorithm is a classical distributed algorithm for matrix multiplication for twodimensional ***,MPI-IO is used for its I/O *** it has been well documented that MPIIO performs poorly in a Lustre file system *** the scale of matrix multiplication increased,this problem trends to be serious,becoming one key factor impacting performance of the *** order to improve the performance of Collective I/O of Cannon's program,we proposed a new aggregation pattern(Stripe-continuous aggregation pattern),which fully considers the stripping mechanism and lock protocol of Lustre file *** theoretical analysis and experimental results show that the pattern can make full use of the capacity of Lustre file system compared with the other patterns,and improve the I/O performance of the Cannon's program efficiently.

关键词： Cannon's algorithm parallel I/O Lustre file system MPI-IO Collective I/O

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Proceedings - 9th IEEE international symposium on parallel and distributed Processing with Applications Workshops, ISPAW 2011 - 2011 international Conference on Advanced Software Engineering, ICASE 2011, 2011 international Conference on Smart Grid and Home Environments, SGH 2011, 2011 international Conference on Green and Smart Disaster Prevention, GSDP 2011

Proceedings - 9th IEEE International Symposium on Parallel a...

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9th IEEE international symposium on parallel and distributed Processing with Applications Workshops, ISPAW 2011 - 2011, ICASE 2011, SGH 2011, GSDP 2011

ISBN: (纸本)9780769544298

The proceedings contain 68 papers. The topics discussed include: trusted computing dynamic attestation by using static analysis based behavior model;evolutionary design of S-box with cryptographic properties;a multi-level grey evaluation model for harms of computer virus;reduce leakage currents in low power SRAM cell structures;concurrent online test architecture for multiple controller blocks with minimum fault latency;modeling and analysis of radiation therapy system with respiratory compensation using uppaal;brushstroke control from image saliency;tomogrphical medical image reconstruction using kalman filter technique;affordable privacy for home smart meters;scheduling of energy storage systems with geographically distributed renewables;selection of model in developing information security criteria on smart grid security system;and two-layer security scheme for AMI system in Taiwan.

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Proceedings - 25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

Proceedings - 25th IEEE International Parallel and Distribut...

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

ISBN: (纸本)9780769543857

The proceedings contain 112 papers. The topics discussed include: power-aware replica placement and update strategies in tree networks;minimum cost resource allocation for meeting job requirements;power and performance management in priority-type cluster computing systems;communication-avoiding QR decomposition for GPU;overlapping computation and communication for advection on hybrid parallel computers;VisIO: enabling interactive visualization of ultra-scale, time series data via high-bandwidth distributed I/O systems;a novel power management for CMP systems in data-intensive environment;characterization of system services and their performance impact in multi-core nodes;automatic recognition of performance idioms in scientific applications;exploiting data similarity to reduce memory footprints;the evaluation of an effective out-of-core run-time system in the context of parallel mesh generation;and a lightweight method for automated design of convergence.

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Quantitative Trait Locus Analysis Using a Partitioned Linear Model on a GPU Cluster

Quantitative Trait Locus Analysis Using a Partitioned Linear...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Peter E. Bailey Tapasya Patki Gregory M. Striemer Ali Akoglu David K. Lowenthal Peter Bradbury Matt Vaughn Liya Wang Stephen Goff Department of Computer Science University of Arizona Tucson USA Department of Electrical and Computer Engineering University of Arizona Tucson USA USDA/ARS and Cornell University USA Texas Advanced Computing Center USA Cold Spring Harbor Laboratory USA IPlant Collaborative USA

Quantitative Trait Locus (QTL) analysis is a statistical technique that allows understanding of the relationship between plant genotypes and the resultant continuous phenotypes in non-constant environments. This requires generation and processing of large datasets, which makes analysis challenging and slow. One approach, which is the subject of this paper, is Partitioned Linear Modeling (PLM), lends itself well to parallelization, both by MPI between nodes and by GPU within nodes. Large input datasets make this parallelization on the GPU non-trivial. This paper compares several candidate integrated MPI/GPU parallel implementations of PLM on a cluster of GPUs for varied data sets. We compare them to a naive implementation and show that while that implementation is quite efficient on small data sets, when the data set is large, data-transfer overhead dominates an all-GPU implementation of PLM. We show that an MPI implementation that selectively uses the GPU for a relative minority of the code performs best and results in a 64 improvement over the MPI/CPU version. As a first implementation of PLM on GPUs, our work serves as a reminder that different GPU implementations are needed, depending on the size of the working set, and that data intensive applications are not necessarily trivially parallelizable with GPUs.

关键词： Graphics processing unit Instruction sets Random access memory Kernel Genetics Registers Memory management

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Automatic Offloading C++ Expression Templates to CUDA Enabled GPUs

Automatic Offloading C++ Expression Templates to CUDA Enable...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jie Chen Balint Joo William Watson III Robert Edwards Jefferson Laboratory The Scientific Computing Group Newport News VA USA Jefferson Laboratory The Theory Center Newport News VA USA

ISBN: (纸本)9781467309745

In the last few years, many scientific applications have been developed for powerful graphics processing units (GPUs) and have achieved remarkable speedups. This success can be partially attributed to high performance host callable GPU library routines that are offloaded to GPUs at runtime. These library routines are based on C/C++-like programming toolkits such as CUDA from NVIDIA and have the same calling signatures as their CPU counterparts. Recently, with the sufficient support of C++ templates from CUDA, the emergence of template libraries have enabled further advancement in code reusability and rapid software development for GPUs. However, Expression Templates (ET), which have been very popular for implementing data parallel scientific software for host CPUs because of their intuitive and mathematics-like syntax, have been underutilized by GPU development libraries. The lack of ET usage is caused by the difficulty of offloading expression templates from hosts to GPUs due to the inability to pass instantiated expressions to GPU kernels as well as the absence of the exact form of the expressions for the templates at the time of coding. This paper presents a general approach that enables automatic offloading of C++ expression templates to CUDA enabled GPUs by using the C++ metaprogramming technique and Just-In-Time (JIT) compilation methodology to generate and compile CUDA kernels for corresponding expression templates followed by executing the kernels with appropriate arguments. This approach allows developers to port applications to run on GPUs with virtually no code modifications. More specifically, this paper uses a large ET based data parallel physics library called QDP++ as an example to illustrate many aspects of the approach to offload expression templates automatically and to demonstrate very good speedups for typical QDP++ applications running on GPUs against running on CPUs using this method of offloading. In addition, this approach of automatic offloa

关键词： Graphics processing unit Arrays Kernel Libraries Vectors Lattices Runtime

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Optimizing MPI Communication on Multi-GPU Systems Using CUDA Inter-Process Communication

Optimizing MPI Communication on Multi-GPU Systems Using CUDA...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： S. Potluri H. Wang D. Bureddy A.K. Singh C. Rosales Dhabaleswar K. Panda Department of Computer Science and Engineering Ohio State University USA Texas Advanced Computing Center USA

ISBN: (纸本)9781467309745

Many modern clusters are being equipped with multiple GPUs per node to achieve better compute density and power efficiency. However, moving data in/out of GPUs continues to remain a major performance bottleneck. With CUDA 4.1, NVIDIA has introduced Inter-Process Communication (IPC) to address data movement overheads between processes using different GPUs connected to the same node. State-of-the-art MPI libraries like MVAPICH2 are being modified to allow application developers to use MPI calls directly over GPU device memory. This improves the programmability for application developers by removing the burden of dealing with complex data movement optimizations. In this paper, we propose efficient designs for intra-node MPI communication on multi-GPU nodes, taking advantage of IPC capabilities provided in CUDA. We also demonstrate how MPI one-sided communication semantics can provide better performance and overlap by taking advantage of IPC and the Direct Memory Access (DMA) engine on a GPU. We demonstrate the effectiveness of our designs using micro-benchmarks and an application. The proposed designs improve GPU-to-GPU MPI Send/Receive latency for 4MByte messages by 79% and achieve 4 times the bandwidth for the same message size. One-sided communication using Put and Active synchronization shows 74% improvement in latency for 4MByte message, compared to the existing Send/Receive based implementation. Our benchmark using Get and Passive Synchronization demonstrates that true asynchronous progress can be achieved using IPC and the GPU DMA engine. Our designs for two-sided and one-sided communication improve the performance of GPULBM, a CUDA implementation of Lattice Boltzmann Method for multiphase flows, by 16%, compared to the performance using existing designs in MVAPICH2. To the best of our knowledge, this is the first paper to provide a comprehensive solution for MPI two-sided and one-sided GPU-to-GPU communication within a node, using CUDA IPC.

关键词： Graphics processing unit Synchronization Performance evaluation Semantics Peer to peer computing Computer architecture Libraries

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A Comprehensive Study of Task Coalescing for Selecting parallelism Granularity in a Two-Stage Bidiagonal Reduction

A Comprehensive Study of Task Coalescing for Selecting Paral...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Azzam Haidar Hatem Ltaief Piotr Luszczek Jack Dongarra Innovative Computing Laboratory University of Tennessee Knoxville TN USA KAUST Supercomputing Laboratory Thuwal Saudi Arabia

We present new high performance numerical kernels combined with advanced optimization techniques that significantly increase the performance of parallel bidiagonal reduction. Our approach is based on developing efficient fine-grained computational tasks as well as reducing overheads associated with their high-level scheduling during the so-called bulge chasing procedure that is an essential phase of a scalable bidiagonalization procedure. In essence, we coalesce multiple tasks in a way that reduces the time needed to switch execution context between the scheduler and useful computational tasks. At the same time, we maintain the crucial information about the tasks and their data dependencies between the coalescing groups. This is the necessary condition to preserve numerical correctness of the computation. We show our annihilation strategy based on multiple applications of single orthogonal reflectors. Despite non-trivial characteristics in computational complexity and memory access patterns, our optimization approach smoothly applies to the annihilation scenario. The coalescing positively influences another equally important aspect of the bulge chasing stage: the memory reuse. For the tasks within the coalescing groups, the data is retained in high levels of the cache hierarchy and, as a consequence, operations that are normally memory-bound increase their ratio of computation to off-chip communication and become compute-bound which renders them amenable to efficient execution on multicore architectures. The performance for the new two-stage bidiagonal reduction is staggering. Our implementation results in up to 50-fold and 12-fold improvement (~130 Gflop/s) compared to the equivalent routines from LAPACK V3.2 and Intel MKL V10.3, respectively, on an eight socket hexa-core AMD Opteron multicore shared-memory system with a matrix size of 24000 × 24000. Last but not least, we provide a comprehensive study on the impact of the coalescing group size in terms of cache ut

关键词： Kernel Tiles Layout Context Multicore processing Symmetric matrices Eigenvalues and eigenfunctions

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Fast and Efficient Graph Traversal Algorithm for CPUs: Maximizing Single-Node Efficiency

Fast and Efficient Graph Traversal Algorithm for CPUs: Maxim...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Jatin Chhugani Nadathur Satish Changkyu Kim Jason Sewall Pradeep Dubey Parallel Computing Laboratory Intel Corporation USA

Graph-based structures are being increasingly used to model data and relations among data in a number of fields. Graph-based databases are becoming more popular as a means to better represent such data. Graph traversal is a key component in graph algorithms such as reachability and graph matching. Since the scale of data stored and queried in these databases is increasing, it is important to obtain high performing implementations of graph traversal that can efficiently utilize the processing power of modern processors. In this work, we present a scalable Breadth-First Search Traversal algorithm for modern multi-socket, multi-core CPUs. Our algorithm uses lock- and atomic-free operations on a cache-resident structure for arbitrary sized graphs to filter out expensive main memory accesses, and completely and efficiently utilizes all available bandwidth resources. We propose a work distribution approach for multi-socket platforms that ensures load-balancing while keeping cross-socket communication low. We provide a detailed analytical model that accurately projects the performance of our single- and multi-socket traversal algorithms to within 5-10% of obtained performance. Our analytical model serves as a useful tool to analyze performance bottlenecks on modern CPUs. When measured on various synthetic and real-world graphs with a wide range of graph sizes, vertex degrees and graph diameters, our implementation on a dual-socket Intel ® Xeon ® X5570 (Intel microarchitecture code name Nehalem) system achieves 1.5X-13.2X performance speedup over the best reported numbers. We achieve around 1 Billion traversed edges per second on a scale-free R-MAT graph with 64M vertices and 2 Billion edges on a dual-socket Nehalem system. Our optimized algorithm is useful as a building block for efficient multi-node implementations and future exascale systems, thereby allowing them to ride the trend of increasing per-node compute and bandwidth resources.

关键词： Sockets Arrays Bandwidth Instruction sets Partitioning algorithms

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