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Modeling and Predicting Performance of High Performance computing Applications on Hardware Accelerators

Modeling and Predicting Performance of High Performance Comp...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Mitesh R. Meswani Laura Carrington Didem Unat Allan Snavely Scott Baden Stephen Poole SDSC University of California San Diego La Jolla CA USA University of California San Diego La Jolla CA USA ORNL Oak Ridge TN USA

ISBN: (纸本)9781467309745

Computers with hardware accelerators, also referred to as hybrid-core systems, speedup applications by offloading certain compute operations that can run faster on accelerators. Thus, it is not surprising that many of top500 supercomputers use accelerators. However, in addition to procurement cost, significant programming and porting effort is required to realize the potential benefit of such accelerators. Hence, before building such a system it is prudent to answer the question 'what is the projected performance benefit from accelerators for the workloads of interest?'. We address this question by way of a performance-modeling framework that predicts realizable application performance on accelerators rapidly and accurately without going to the considerable effort of porting and tuning. The modeling framework first automatically identifies commonly found compute patterns in scientific applications which we term idioms, which may benefit by accelerator technology. Next the framework models the predicted speedup of those idioms if they were to be ported to and run on hardware accelerators. As a proof of concept we characterize two kinds of accelerators 1) the FPGA accelerators on a Convey HC-1 system and 2) an NVIDIA FERMI GPU accelerator. We model performance of the idioms gather/scatter and stream and our predictions show that where these occur in two full-scale HPC applications, Milc and HYCOM, gather/scatter speeds up by as much as 15X, and stream by as much as 14X, whereas the overall compute time of Milc improves by 3.4% and HYCOM by 20%.

关键词： Field programmable gate arrays Predictive models Hardware Graphics processing unit Computational modeling Bandwidth Performance evaluation

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Improving parallel IO Performance of Cell-based AMR Cosmology Applications

Improving Parallel IO Performance of Cell-based AMR Cosmolog...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Yongen Yu Douglas H. Rudd Zhiling Lan Nickolay Y. Gnedin Andrey Kravtsov Jingjin Wu Department of Computer Science Illinois Institute of Technology Chicago IL USA Yale Center for Astronomy and Astrophysics Yale University New Heaven CT USA Theoretical Astrophysics Group Fenni National Accelerator Laboratory Batavia IL USA Department of Astronomy and Astrophysics University of Chicago Chicago IL USA

ISBN: (纸本)9781467309752

To effectively model various regions with different resolutions, adaptive mesh refinement (AMR) is commonly used in cosmology simulations. There are two well-known numerical approaches towards the implementation of AMR based cosmology simulations: block-based AMR and cell-based AMR. While many studies have been conducted to improve performance and scalability of block-structured AMR applications, little work has been done for cell-based simulations. In this study, we present a parallel IO design for cell-based AMR cosmology applications, in particular, the ART(Adaptive Refinement Tree) code. First, we design a new data format that incorporates a space filling curve to map between spatial and on-disk locations. This indexing not only enables concurrent IO accesses from multiple application processes, but also allows users to extract local regions without significant additional memory, CPU or disk space overheads. Second, we develop a flexible N-M mapping mechanism to harvest the benefits of N-N and N-1 mappings where N is number of application processes and M is a user-tunable parameter for number of files. It not only overcomes the limited bandwidth issue of an N-1 mapping by allowing the creation of multiple files, but also enables users to efficiently restart the application at a variety of computing scales. Third, we develop a user-level library to transparently and automatically aggregate small IO accesses per process to accelerate IO performance. We evaluate this new parallel IO design by means of real cosmology simulations on production HPC system at TACC. Our preliminary results indicate that it can not only provide the functionality required by scientists (e.g., effective extraction of local regions and flexible process-to file mapping), but also significantly improve IO performance.

关键词： Indexes Computational modeling Adaptation models Subspace constraints Layout Numerical models Data models

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SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory

SEL-TM: Selective Eager-Lazy Management for Improved Concurr...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Lihang Zhao Woojin Choi Jeff Draper Information Sciences Institute University of Southern California Marina del Rey CA USA

Hardware Transactional Memory (HTM) systems implement version management and conflict detection in hardware to guarantee that each transaction is atomic and executes in isolation. In general, HTM implementations fall into two categories, namely, eager systems and lazy systems. Lazy systems have been shown to exploit more concurrency from potentially conflicting transactions. However, lazy systems manage a transaction's entire write set lazily, which gives rise to two main disadvantages: (a) a complex cache protocol and implementation are required to maintain the speculative modifications, and, (b) the latency of committing the entire write set often leads to severe performance degradation of the whole system. It is observed in a wide range of workloads that more than 55% of the transaction aborts are due to conflicts on only three memory blocks. Thus we argue that an eager HTM system can achieve the same level of concurrency as lazy systems by managing only a small portion of a transaction's write set lazily. In this paper, we present Selective-Eager-Lazy HTM (SEL-TM), a new HTM implementation to adopt complementary version management schemes within a transaction whose write set is divided into eagerly- and lazily-managed memory addresses at runtime. An intelligent hardware scheme is designed to select the memory addresses for lazy management as well as determining whether each dynamic instance of a transaction benefits from hybrid management. Experimental results using the STAMP benchmarks show that, on average, SEL-TM improves performance by 14% over an eager system and 22% over a lazy system. The speedup demonstrates that our design is capable of harvesting the concurrency benefit of lazy version management while avoiding some of the performance penalties in lazy HTMs.

关键词： Memory management Concurrent computing Hardware Instruction sets Runtime Pathology Buffer storage

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2011 IEEE international symposium on parallel and distributed Processing, Workshops and Phd Forum, IPDPSW 2011

2011 IEEE International Symposium on Parallel and Distribute...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

ISBN: (纸本)9780769543857

The proceedings contain 267 papers. The topics discussed include: an agent-based approach to reconciling data heterogeneity in cyber-physical systems;NVCR: a transparent checkpoint-restart library for NVIDIA CUDA;use of Internet embedding tools for heterogeneous resources aggregation;a high-level power model for MPSoC on FPGA;modular framework for multi-level multi-device MPSoC simulation;a heterogeneous multicore system on chip with run-time reconfigurable virtual FPGA architecture;a scalable microarchitecture design that enables dynamic code execution for variable-issue clustered processors;CRM: configurable range memory for fast reconfigurable computing;tuple spaces in hardware for accelerated implicit routing;an FPGA-based accelerator to speed-up matrix multiplication of floating point operations;the SecretBlaze: a configurable and cost-effective open-source soft-core processor;and bitonic sorting on dynamically reconfigurable architectures.

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Proceedings - 6th international symposium on parallel computing in Electrical Engineering, PARELEC 2011

Proceedings - 6th International Symposium on Parallel Comput...

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6th international symposium on parallel computing in Electrical Engineering, PARELEC 2011

ISBN: (纸本)9780769543970

The proceedings contain 33 papers. The topics discussed include: static average case analysis fork-join framework programs based on MOQA method;parallelizing a coarse grain graph search problem based upon LDPC codes on a supercomputer;an approach towards automation firmware modeling for an exploration and evaluation of efficient parallelization alternatives;communication on the fly for hierarchical systems of chip multi-processors;optimizing heterogeneous 3D networks-on-chip;a dynamic core grouping approach to improve raw architecture many-core processor performance;event-driven scheduling for parallel stream processing;optimal placement of the wind generators in the medium voltage power grid;potential of general purpose graphic processing unit for energy management system;goal-oriented adaptive workload management for irregular applications;and distributed program control flow and behavior governed by global states monitoring.

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Exploring the Scope of the InfiniBand Congestion Control Mechanism

Exploring the Scope of the InfiniBand Congestion Control Mec...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Ernst Gunnar Gran Sven-Arne Reinemo Olav Lysne Tor Skeie Eitan Zahavi Gilad Shainer Simula Research Laboratory Fornebu Norway Mellanox Technol. Israel

ISBN: (纸本)9781467309752

In a loss less interconnection network, network congestion needs to be detected and resolved to ensure high performance and good utilization of network resources at high network load. If no countermeasure is taken, congestion at a node in the network will stimulate the growth of a congestion tree that not only affects contributors to congestion, but also other traffic flows in the network. Left untouched, the congestion tree will block traffic flows, lead to underutilization of network resources and result in a severe drop in network performance. The InfiniBand standard specifies a congestion control (CC) mechanism to detect and resolve congestion before a congestion tree is able to grow and, by that, hamper the network performance. The InfiniBand CC mechanism includes a rich set of parameters that can be tuned in order to achieve effective CC. Even though it has been shown that the CC mechanism, properly tuned, is able to improve both throughput and fairness in an interconnection network, it has been questioned whether the mechanism is fast enough to keep up with dynamic network traffic, and if a given set of parameter values for a topology is robust when it comes to different traffic patterns, or if the parameters need to be tuned depending on the applications in use. In this paper we address both these questions. Using the three-stage fat-tree topology from the Sun Data center InfiniBand Switch 648 as a basis, and a simulator tuned against CC capable InfiniBand hardware, we conduct a systematic study of the efficiency of the InfiniBand CC mechanism as the network traffic becomes increasingly more dynamic. Our studies show that the InfiniBand CC, even when using a single set of parameter values, performs very well as the traffic patterns becomes increasingly more dynamic, outperforming a network without CC in all cases. Our results show throughput increases varying from a few percent, to a seventeen-fold increase.

关键词： Vegetation Switches Peer to peer computing Network topology Multiprocessor interconnection Standards

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Adapting Matrix-Vector-Multiply Wavefront Reconstruction to SMP

Adapting Matrix-Vector-Multiply Wavefront Reconstruction to ...

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The Eleventh international symposium on distributed computing and Applications to Business,Engineering and Science(DCABES2012)(第十一届分布式计算及其应用国际学术研讨会)(原名:电子商务、工程及科学领域的分布式计算和应用国际学术研讨会)

作者： Haotian Zhang Mei Li Luchun Zhou The Key Laboratory on Adaptive Optics Institute of Optics and Electronics CAS ChengduChina

In adaptive optics systems,the process time of wavefront controller is a critical *** a fixed frame rate,decreasing the process time results in higher control *** the process steps of a wavefront controller,wavefront reconstruction is a time consuming *** this paper,we parallelized wavefront reconstruction algorithm on a cutting edge shared-memory eight-core DSP to reduce process *** conducted experiment shows that even using the most computation and memory intensive matrix-vectormultiply(MVM)reconstruction algorithm,performance requirements can be met with reconstruction latency around 130us in a 913 actuators AO *** parallelization of the reconstruction algorithm,it's possible to apply high frame rate in the system and easy to scale up to larger systems with more actuators.

关键词： Adaptive Optics Wavefront reconstruction DSP parallel processing

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Designing Network Failover and Recovery in MPI for Multi-Rail InfiniBand Clusters

Designing Network Failover and Recovery in MPI for Multi-Rai...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： S. Pai Raikar H. Subramoni K. Kandalla J. Vienne Dhabaleswar K. Panda Department of Computer Science and Engineering Ohio State University Columbus OH USA

ISBN: (纸本)9781467309745

The emerging trends of designing commodity-based supercomputing systems have a severe detrimental impact on the Mean-Time-Between-Failures (MTBF). The MTBF for typical HEC installations is currently estimated to be between eight hours and fifteen days [1]. Failures in the interconnect fabric account for a fair share of the total failures occurring in such systems. This will continue to degrade as system sizes become larger. Thus, it is highly desirable that next generation system architectures and software environments provide sophisticated network level fault-tolerance and fault-resilient solutions. In the past few years, the number of cores on processors has increased dramatically. To make efficient use of these machines it is necessary to provide the required bandwidth to all the cores. To keep up with the multi-core trend, current generation supercomputers and clusters are designed with multiple network cards (rails) to provide enhanced data transfer capabilities. Besides providing enhanced performance, such multi-rail networks can also be leveraged to provide network level fault resilience. This paper presents a design for a failover mechanism in a multi-rail scenario, for handling network failures and their recovery without compromising on performance. In a general message passing scenario, whenever there is a network failure, the entire job aborts. Our design allows the job to continue even when a network failure occurs, by using the remaining rails for communication. Once the rail recovers from the failure, we also propose a protocol to re-establish connections on that rail and resume normal operations. We experimentally demonstrate that our implementation adds very little overhead and is able to deliver good performance which is comparable to that of the other rails running in isolation. We also show that the recovery is immediate and is associated with no additional overhead. We also depict sustenance and reliability of the design by running application be

关键词： Rails Libraries Fault tolerance Fault tolerant systems Peer to peer computing Servers Benchmark testing

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parallelized Force-Directed Edge Bundling on the GPU

Parallelized Force-Directed Edge Bundling on the GPU

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作者： Delu Zhu Danhuai Guo Kaichao Wu Yuanmin Chen Computer Network Information Center Chinese Academy of Sciences Graduate University of Chinese Acade Computer Network Information Center Chinese Academy of Sciences Beijing100190China China Internet Network Information Center DNSLAB Beijing 100190China

How to draw large scale spatial interaction data clearly and quickly is a challenge in high performance data visualization research and application ***-Directed Edge Bundling(FDEB)helps display graph clearly with significant clutter reduction,but with high time *** paper presents a parallelized FDEB on the GPU(GPUFDEB),which reforms FDEB and achieves a balanced partitioning of data and calculation to suit computation on the ***-FDEB addresses the problem of high time complexity and accelerates FDEB by an order of magnitude.

关键词： GPU parallel FDEB visualization CUDA

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Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth

Robust SIMD: Dynamically Adapted SIMD Width and Multi-Thread...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Jiayuan Meng Jeremy W. Sheaffer Kevin Skadron Leadership Computing Facility Division Argonne National Laboratory Argonne IL USA Department of Computer Science University of Virginia Charlottesville VA USA

Architectures that aggressively exploit SIMD often have many data paths execute in lockstep and use multi-threading to hide latency. They can yield high through-put in terms of area- and energy-efficiency for many data-parallel applications. To balance productivity and performance, many recent SIMD organizations incorporate implicit cache hierarchies. Examples of such architectures include Intel's MIC, AMD's Fusion, and NVIDIA's Fermi. However, unlike software-managed streaming memories used in conventional graphics processors (GPUs), hardware-managed caches are more disruptive to SIMD execution, therefore the interaction between implicit caching and aggressive SIMD execution may no longer follow the conventional wisdom gained from streaming memories. We show that due to more frequent memory latency divergence, lower latency in non-L1 data accesses, and relatively unpredictable L1 contention, cache hierarchies favor different SIMD widths and multi-threading depths than streaming memories. In fact, because the above effects are subject to runtime dynamics, a fixed combination of SIMD width and multi-threading depth no longer works ubiquitously across diverse applications or when cache capacities are reduced due to pollution or power saving. To address the above issues and reduce design risks, this paper proposes Robust SIMD, which provides wide SIMD and then dynamically adjusts SIMD width and multi-threading depth according to performance feedback. Robust SIMD can trade wider SIMD for deeper multi-threading by splitting a wider SIMD group into multiple narrower SIMD groups. Compared to the performance generated by running every benchmark on its individually preferred SIMD organization, the same Robust SIMD organization performs similarly -- sometimes even better due to phase adaptation -- and out per-forms the best fixed SIMD organization by 17%. When D-cache capacity is reduced due to runtime disruptiveness, Robust SIMD offers graceful performance degradation, with

关键词： Instruction sets Robustness Organizations Runtime Vectors Hardware Message systems

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