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A framework for automated performance tuning and code verification on GPU computing platforms

A framework for automated performance tuning and code verifi...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Gehrke, Allison S. Ra, Ilkyeun Connors, Daniel A. Dept. of Computer Science and Engineering University of Colorado Denver Denver CO 80204 United States Dept. of Electrical Engineering University of Colorado Denver Denver CO 80204 United States

ISBN: (纸本)9780769543857

Emerging multi-core processor designs create a computing paradigm capable of advancing numerous scientific areas, including medicine, data mining, biology, physics, and earth sciences. However, the trends in multi-core hardware technology have advanced far ahead of the advances in software technology and programmer productivity. For the most part, current scientists only leverage multi-core and GPU (Graphical Processing Unit) computing platforms after painstakingly uncovering the inherent task and data-level parallelism in their application. In many cases, the development does not realize the full potential of the parallel hardware. There exists an opportunity to meet the challenges in optimally mapping scientific application domains to multi-core computer systems through the use of compile-time and link-time optimization strategies. We are exploring a code compilation framework that automatically generates and tunes numerical solver codes for optimal performance on graphical processing units. The framework advances computational simulation in kinetic modeling by significantly reducing the execution time of scientific simulations and enabling scientists to compare results to previous models and to extend, modify, and test new models without code changes. © 2011 IEEE.

关键词： Graphics processing unit

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Building an online computing service over volunteer grid resources

Building an online computing service over volunteer grid res...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Silberstein, Mark Technion Israel

ISBN: (纸本)9780769543857

Volunteer computing grids have traditionally been used for massively parallel workloads, such as processing data from large scientific experiments. We argue that the domain of volunteer grids can be extended well beyond this specific niche, by enhancing them with built-in mechanisms for integration with with standard clusters, grids and clouds, to compensate for unexpected fluctuations in resource availability and quality of service. The resulting capabilities for on-demand dynamic expansion of the resource pool, together with sophisticated scheduling mechanisms will turn volunteer grids into a powerful execution platform for on-line interactive computing services. We will show our experience with the GridBoT system, which implements these ideas. GridBoT is part of a production high performance online service for genetic linkage analysis, called Superlink-online. The system enables anyone with the Internet access to submit genetic data, and easily and quickly analyze it as if using a supercomputer. The analyses are automatically parallelized and executed via GridBoT on over 45,000 non-dedicated machines from the Superlink@Technion volunteer grid, as well as on 9 other grids and clouds, including the Aamazon EC2. Since 2009 the system has served more than 300 geneticists from leading research institutions worldwide, and executed over 6500 different real analysis runs, with about 10 million tasks consumed over 420 CPU years. © 2011 IEEE.

关键词： Supercomputers

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Multi-scale analysis of large distributed computing systems

Multi-scale analysis of large distributed computing systems

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3rd international Workshop on Large-Scale System and Application Performance, LSAP'11, Co-located with 20th international ACM symposium on High-Performance parallel and distributed computing, HPDC 2011

作者： Schnorr, Lucas Mello Legrand, Arnaud Vincent, Jean-Marc INRIA MESCAL CNRS LIG Grenoble France

ISBN: (纸本)9781450307031

Large scale distributed systems are composed of many thousands of computing units. Today's examples of such systems are grid, volunteer and cloud computing platforms. Generally, their analyses are done through monitoring tools that gather resource information like processor or network utilization, providing high-level statistics and basic resource usage traces. Such approaches are recognized as rather scalable but are unfortunately often insufficient to detect or fully understand unexpected behavior. In this paper, we investigate the use of more detailed tracing techniques - commonly used in parallel computing - in distributed systems. Finely analyzing the behavior of such systems comprising thousands of resources over several months may seem infeasible. Yet, we show that the resulting trace can be analyzed using tools that enable to easily zoom in and out on selected area of space and time. We use the BOINC volunteer computing system as a basis of this study. Since detailed activity traces of the BOINC clients are not available yet, we rely instead on traces obtained through a BOINC simulator developed with the SimGrid toolkit and which uses as input real availability trace files from the Seti@Home BOINC project. We show that the analysis of such detailed resource utilization traces provides several non-trivial insights about the whole system and enables the discovery of unexpected behavior. © 2011 ACM.

关键词： Grid computing

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A graph model for minimizing the storage overhead of distributing data for the parallel solution of two-phase flows

A graph model for minimizing the storage overhead of distrib...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Fortmeier, Oliver Bastea, Alin A. Bücker, H. Martin RWTH Aachen University Institute for Scientific Computing Aachen Germany

ISBN: (纸本)9780769543857

We consider a finite element method for the parallel solution of two-phase flow problems using a level set approach. Here, two systems of equations result from the discretization of the governing partial differential equations. Rather than investigating the solution of these systems, we focus on finding a data distribution for their assembly. We formulate a new combinatorial problem that minimizes the overhead in storage requirement to represent the systems while, at the same time, balancing the computational effort to assemble these systems in parallel. We model this problem by introducing a weighted undirected graph. We then transform the problem to a (standard) graph partitioning problem in which a weighted sum of certain edges is minimized subject to balancing a weighted sum of all vertices. Numerical experiments are carried out illustrating the feasibility of the new approach for an application using up to 512 processes of a cluster of quad-core processors. © 2011 IEEE.

关键词： Two phase flow

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Predictive and distributed routing balancing on high-speed cluster networks

Predictive and distributed routing balancing on high-speed c...

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23rd international symposium on Computer Architecture and High Performance computing, SBAC-PAD 2011

作者： Castillo, Carlos Núñez Lugones, Diego Franco, Daniel Luque, Emilio Computer Architecture and Operating Systems Department Universitat Autònoma de Barcelona Spain

ISBN: (纸本)9780769545738

In high performance clusters current parallel application communication needs such as traffic pattern, communication volume, etc., change along time and are difficult to know in advance. Such needs often exceed or do not match available resources causing resource use imbalance, network congestion, throughput reduction and message latency increase, thus degrading the overall system performance. Studies on parallel applications show repetitive behavior that can be characterized by a set of representative phases. This work presents a Predictive and distributed Routing Balancing (PRDRB) technique, a new method developed to gradually control network congestion, based on paths expansion, traffic distribution, applications pattern repetitiveness and speculative adaptive routing, in order to maintain low latency values. PRDRB monitors messages latencies on routers and logs solutions to congestion, to quickly respond in future similar situations. Traffic congestion experiments were conducted in order to evaluate the performance of the method, and improvements were observed. © 2011 IEEE.

关键词： Traffic congestion

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distributed results checking for mapreduce in Volunteer computing

Distributed results checking for mapreduce in Volunteer Comp...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Moca, Mircea Silaghi, Gheorghe Cosmin Fedak, Gilles Babes.-Bolyai University Cluj-Napoca Romania INRIA Université de Lyon France

ISBN: (纸本)9780769543857

MapReduce is a promising approach to support data-intensive applications on Volunteer computing Systems. Existent middleware like BitDew allows running MapReduce applications in a Desktop Grid environment. If the Desktop Grid is deployed in the Internet under the Volunteer computing paradigm, it harnesses untrustable, volatile and heterogeneous resources and the results produced by MapRe-duce applications can be subject of sabotage. However, the implementation of large-scale MapReduce presents significant challenges with respect to the state of the art in Desktop Grid. A key issue is the design of the result certification, an operation needed to verify that malicious volunteers do not tamper with the results of computations. Because the volume of data produced and processed is so large that cannot be sent back to the server, the result certification cannot be centralized as it is currently implemented in Desktop Grid systems. In this paper we present a distributed result checker based on the Majority Voting method. We evaluate the efficiency of our approach using a model for characterizing errors and sabotage in the MapReduce paradigm. With this model, we can compute the aggregated probability with which a MapReduce implementation produces an erroneous result. The challenge is to capture the aggregated probability for the entire system, composed from probabilities resulted from the two phases of computation: Map and Reduce. We provide a detailed analysis on the performance of the result verification method and also discuss the generated overhead of managing security. We also give guidelines about how the result verification phase should be configured, given a MapReduce application. © 2011 IEEE.

关键词： MapReduce

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Accelerating protein sequence search in a heterogeneous computing system

Accelerating protein sequence search in a heterogeneous comp...

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

作者： Xiao, Shucai Lin, Heshan Feng, Wu-Chun Department of Electrical and Computer Engineering Virginia Tech. Blacksburg VA 24061 United States Department of Computer Science Virginia Tech. Blacksburg VA 24061 United States

ISBN: (纸本)9780769543857

The "Basic Local Alignment Search Tool" (BLAST) is arguably the most widely used computational tool in bioinformatics. However, the computational power required for routine BLAST analysis has been outstripping Moore's Law due to the exponential growth in the size of the genomic sequence databases that BLAST searches on. To address the above issue, we propose the design and optimization of the BLAST algorithm for searching protein sequences (i.e., BLASTP) in a heterogeneous computing system. The end result is a BLASTP implementation that delivers a seven-fold speedup over the sequential BLASTP for the most computationally intensive phase (i.e., hit detection and ungapped extension) on a NVIDIA Fermi C2050 GPU. In addition, when pipelining the processing on a dual-core CPU and the NVIDIA Fermi GPU, our implementation can achieve a six-fold speedup for the overall program execution. © 2011 IEEE.

关键词： Graphics processing unit

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computing the phylogenetic likelihood function out-of-core

Computing the phylogenetic likelihood function out-of-core

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Izquierdo-Carrasco, Fernando Stamatakis, Alexandros Exelixis Lab. Scientific Computing Group Heidelberg Institute for Theoretical Studies D-69118 Heidelberg Germany

ISBN: (纸本)9780769543857

The computation of the phylogenetic likelihood function for reconstructing evolutionary trees from molecular sequence data is both memory- and compute-intensive. Based on our experience with the user community of RAxML, memory-shortages (as opposed to CPU time limitations) are currently the prevalent problem regarding resource availability, that is, lack of memory hinders large-scale biological analyses. To this end, we study the performance of an out-of-core execution of the phylogenetic likelihood function by means of a proof-of-concept implementation in RAxML. We find that RAM miss rates are below 10%, even if only 5% of the required data structures are held in RAM. Moreover, we show that our proof-of-concept implementation runs more than 5 times faster than the respective standard implementation when paging is used. The concepts presented here can be applied to all programs that rely on the phylogenetic likelihood function and can contribute significantly to enabling the computation of whole-genome phylogenies. © 2011 IEEE.

关键词： Phylogenetic

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distributed program control flow and behaviour governed by global states monitoring

Distributed program control flow and behaviour governed by g...

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6th international symposium on parallel computing in Electrical Engineering, PARELEC 2011

作者： Tudruj, Marek Borkowski, Janusz Kopanski, Damian Smyk, Adam Laskowski, Eryk Masko, Lukasz Polish-Japanese Institute of Information Technology ul. Koszykowa 86 02-008 Warsaw Poland Institute of Computer Science Polish Academy of Sciences ul. Ordona 21 01-237 Warsaw Poland

ISBN: (纸本)9780769543970

A new framework for designing evolved program execution control in distributed programs is discussed in the paper. The framework provides an infrastructure for designing distributed program control based on monitoring of global application states. Global control constructs are proposed which logically bind distributed program modules and define the flow of control dependent on the monitoring of global application states. Such control can be organized in programs at the process and thread levels. Special processes and threads called synchronizers collect state information from application modules, construct strongly consistent global states and evaluate control predicates on global states. Based on this evaluation control signals are sent to processes and threads to define inter module flow of control and to influence the internal module behavior. The proposed constructs are incorporated into the framework as a graphical API which is compiled into C/C++ programs with the MPI2, pthreads and Open Mp libraries for communication. © 2011 IEEE.

关键词： Application programs

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Just-in-time instruction set extension - Feasibility and limitations for an FPGA-based reconfigurable ASIP architecture

Just-in-time instruction set extension - Feasibility and lim...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Grad, Mariusz Plessl, Christian Paderborn Center for Parallel Computing University of Paderborn Germany

ISBN: (纸本)9780769543857

In this paper, we study the feasibility of moving the instruction set customization process for reconfigurable ASIPs to runtime under the precondition that current FPGA devices and tools are used. To this end we propose a tool flow for just-in-time ASIP customization which identifies suitable custom instructions to accelerate arbitrary binary applications that execute on a virtual machine. The tool flow targets our previously introduced Woolcano reconfigurable ASIP architecture, which augments the PowerPC core in a Xilinx Virtex 4FX CPU with runtime reconfigurable instructions. We evaluate the tool flow with a comprehensive set of applications from the SPEC2006, SPEC2000, MiBench, and SciMark2 benchmark suites and compare the speedups that can be achieved with the overhead of the complete ASIP specialization process. We show that an average speedup of 5× can be achieved for benchmarks from the embedded computing domain. The overhead of custom instruction identification and hardware generation for these benchmarks is less than 50 minutes and will be compensated if the applications execute for more than 2 hours. Finally, we evaluate caching strategies to reduce the time until this break even point is reached. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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