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Predicting node failure in high performance computing systems from failure and usage logs

Predicting node failure in high performance computing system...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Nakka, Nithin Agrawal, Ankit Choudhary, Alok Coordinated Science Laboratory University of Illinois at Urbana-Champaign 1308 W. Main St. Urbana IL 61801 United States Department of Electrical Engineering and Computer Science Northwestern University Tech Inst. Bldg. 2145 Sheridan Rd. Evanston IL 60202 United States

ISBN: (纸本)9780769543857

In this paper, we apply data mining classification schemes to predict failures in a high performance computer system. Failure and Usage data logs collected on supercomputing clusters at Los Alamos National Laboratory (LANL) were used to extract instances of failure information. For each failure instance, past and future failure information is accumulated - time of usage, system idle time, time of unavailability, time since last failure, time to next failure. We performed two separate analyses, with and without classifying the failures based on their root cause. Based on this data, we applied some popular decision tree classifiers to predict if a failure would occur within 1 hour. Our experiments show that our prediction system predicts failures with a high-degree of precision up to 73% and recall of about 80%. We also observed that employing the usage data along with the failure data has improved the accuracy of prediction. © 2011 IEEE.

关键词： Forecasting

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parallelization strategies for Ant Colony Optimisation on GPUs

Parallelization strategies for Ant Colony Optimisation on GP...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Cecilia, José M. García, José M. Ujaldón, Manuel Nisbet, Andy Amos, Martyn Computer Architecture Department University of Murcia 30100 Murcia Spain Computer Architecture Department University of Malaga 29071 Málaga Spain Novel Computation Group Division of Computing and IS Manchester Metropolitan University Manchester M1 5GD United Kingdom

ISBN: (纸本)9780769543857

Ant Colony Optimisation (ACO) is an effective population-based meta-heuristic for the solution of a wide variety of problems. As a population-based algorithm, its computation is intrinsically massively parallel, and it is therefore theoretically well-suited for implementation on Graphics Processing Units (GPUs). The ACO algorithm comprises two main stages: Tour construction and Pheromone update. The former has been previously implemented on the GPU, using a task-based parallelism approach. However, up until now, the latter has always been implemented on the CPU. In this paper, we discuss several parallelisation strategies for both stages of the ACO algorithm on the GPU. We propose an alternative data-based parallelism scheme for Tour construction, which fits better on the GPU architecture. We also describe novel GPU programming strategies for the Pheromone update stage. Our results show a total speed-up exceeding 28× for the Tour construction stage, and 20× for Pheromone update, and suggest that ACO is a potentially fruitful area for future research in the GPU domain. © 2011 IEEE.

关键词： Graphics processing unit

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Automated, parallel optimization algorithms for stochastic functions

Automated, parallel optimization algorithms for stochastic f...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Chahal, Dheeraj Stuart, Steven J. Goasguen, Sebastian Trout, Colin J. School of Computing Clemson University Clemson SC 29634 United States Department of Chemistry Clemson University Clemson SC 29634 United States Department of Chemistry Saint Francis University Loretto PA 15940 United States

ISBN: (纸本)9780769543857

We propose a hierarchical framework and new parallel algorithms for stochastic function optimization under conditions where the function to be optimized is subject to random noise, the variance of which decreases with sampling time. This is the situation expected for many real-world and simulation applications where results are obtained from sampling, and contain experimental error or random noise. Our new optimization algorithms are based on a downhill simplex algorithm, with extensions that alter the timing of simplex operations based on the level of noise in the function evaluations. Three proposed optimization methods, which we term maxnoise, point-to-point comparison, and a combination of these two, are tested on the Rosenbrock function and found to be better than previous stochastic optimization methods. The parallel framework implementing the optimization algorithms is also new, and is based on a master-worker architecture where each worker runs a massively parallel program. The parallel implementation allows the sampling to proceed independently on multiple processors, and is demonstrated to scale well up to over 100 vertices. It is highly suitable for clusters with an ever increasing number of cores per node. The new methods have been applied successfully to the reparameterization of the TIP4P water model, achieving thermodynamic and structural results for liquid water that are as good as or better than the original model, with the advantage of a fully automated parameterization process. © 2011 IEEE.

关键词： Linear programming

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Two-stage tridiagonal reduction for dense symmetric matrices using tile algorithms on multicore architectures

Two-stage tridiagonal reduction for dense symmetric matrices...

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

作者： Luszczek, Piotr Ltaief, Hatem Dongarra, Jack Innovative Computing Laboratory University of Tennessee Knoxville TN 37996 United States

ISBN: (纸本)9780769543857

While successful implementations have already been written for one-sided transformations (e.g., QR, LU and Cholesky factorizations) on multicore architecture, getting high performance for two-sided reductions (e.g., Hessenberg, tridiagonal and bidiagonal reductions) is still an open and difficult research problem due to expensive memory-bound operations occurring during the panel factorization. The processor-memory speed gap continues to widen, which has even further exacerbated the problem. This paper focuses on an efficient implementation of the tridiagonal reduction, which is the first algorithmic step toward computing the spectral decomposition of a dense symmetric matrix. The original matrix is translated into a tile layout i.e., a high performance data representation, which substantially enhances data locality. Following a two-stage approach, the tile matrix is then transformed into band tridiagonal form using compute intensive kernels. The band form is further reduced to the required tridiagonal form using a left-looking bulge chasing technique to reduce memory traffic and memory contention. A dependence translation layer associated with a dynamic runtime system allows for scheduling and overlapping tasks generated from both stages. The obtained tile tridiagonal reduction significantly outperforms the state-of-the-art numerical libraries (10X against multithreaded LAPACK with optimized MKL BLAS and 2.5X against the commercial numerical software Intel MKL) from medium to large matrix sizes. © 2011 IEEE.

关键词： Scheduling algorithms

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A history-based performance prediction model with profile data classification for automatic task allocation in heterogeneous computing systems

A history-based performance prediction model with profile da...

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9th IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2011

作者： Sato, Katsuto Komatsu, Kazuhiko Takizawa, Hiroyuki Kobayashi, Hiroaki Graduate School of Information Sciences Tohoku University Sendai Japan Cyberscience Center Tohoku University Sendai Japan

ISBN: (纸本)9780769544281

In this paper, we propose a runtime performance prediction model for automatic selection of accelerators to execute kernels in OpenCL. The proposed method is a history-based approach that uses profile data for performance prediction. The profile data are classified into some groups, from each of which its own performance model is derived. As the execution time of a kernel depends on some runtime parameters such as kernel arguments, the proposed method first identifies parameters affecting the execution time by calculating the correlation between each parameter and the execution time. A parameter with weak correlation is used for the classification of the profile data and the selection of the performance prediction model. A parameter with strong correlation is used for building a linear model for the prediction of the kernel execution time by using only the classified profile data. Experimental results clearly indicate that the proposed method can achieve more accurate performance prediction than conventional history-based approaches because of the profile data classification. © 2011 IEEE.

关键词： Forecasting

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I/O-optimal distribution sweeping on private-cache chip multiprocessors

I/O-optimal distribution sweeping on private-cache chip mult...

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

作者： Ajwani, Deepak Sitchinava, Nodari Zeh, Norbert Centre for Unified Computing University College Cork Cork Ireland MADALGO Department of Computer Science University of Aarhus Aarhus Denmark Faculty of Computer Science Dalhousie University Halifax NS Canada

ISBN: (纸本)9780769543857

The parallel external memory (PEM) model has been used as a basis for the design and analysis of a wide range of algorithms for private-cache multi-core architectures. As a tool for developing geometric algorithms in this model, a parallel version of the I/O-efficient distribution sweeping framework was introduced recently, and a number of algorithms for problems on axis-aligned objects were obtained using this framework. The obtained algorithms were efficient but not optimal. In this paper, we improve the framework to obtain algorithms with the optimal I/O complexity of O(sort P(N) + K/PB) for a number of problems on axis-aligned objects, P denotes the number of cores/processors, B denotes the number of elements that fit in a cache line, N and K denote the sizes of the input and output, respectively, and sort P(N) denotes the I/O complexity of sorting N items using P processors in the PEM model. To obtain the above improvement, we present a new one-dimensional batched range counting algorithm on a sorted list of ranges and points that achieves an I/O complexity of O((N + K)/PB), where K is the sum of the counts of all the ranges. The key to achieving efficient load balancing among the processors in this algorithm is a new method to count the output without enumerating it, which might be of independent interest. © 2011 IEEE.

关键词： Computational geometry

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ScienceCloud'11 - Proceedings of the 2nd international Workshop on Scientific Cloud computing

ScienceCloud'11 - Proceedings of the 2nd International Works...

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2nd international Workshop on Scientific Cloud computing, ScienceCloud'11, Co-located with 20th international ACM symposium on High-Performance parallel and distributed computing, HPDC 2011

ISBN: (纸本)9781450306997

The proceedings contain 8 papers. The topics discussed include: the case for being lazy: how to leverage lazy evaluation in MapReduce;cloud resource usage - extreme distributions invalidating traditional capacity planning models;experiences using cloud computing for a scientific workflow application;adaptive rate stream processing for smart grid applications on clouds;an automated approach to cloud storage service selection;Neptune: a domain specific language for deploying HPC software on cloud platforms;Magellan: experiences from a science cloud;and Cumulus: an open source storage cloud for science.

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A software-pipelined approach to multicore execution of timing predictable multi-threaded hard real-time tasks

A software-pipelined approach to multicore execution of timi...

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IEEE international symposium on Object, Component, Service-Oriented Real-Time distributed computing

作者： Paolieri, Marco Quiñones, Eduardo Cazorla, Francisco J. Wolf, Julian Ungerer, Theo Uhrig, Sascha Petrov, Zlatko Spain Spain Universitat Politecnica de Catalunya Spain University of Augsburg Germany Technical University Dortmund Germany Honeywell International s.r.o. Czech Republic

ISBN: (纸本)9780769543680

Multicore processors can deliver higher performance than single-core processors by exploiting thread level parallelism (TLP): applications are split into independent threads, each of which is mapped into a different core, reducing the execution time and potentially its worst-case execution time (WCET). Unfortunately, inter-thread interferences generated by simultaneous accesses to shared resources from different threads may completely destroy the performance benefits brought by TLP. This paper proposes a software/hardware cache partitioning approach that reduces the inter-thread memory interferences generated in hard real-time software-pipelined parallel applications. Our results show that our approach effectively reduces memory interferences, while still guaranteeing a predictable timing behaviour, achieving a WCET estimation reduction of 28% for a software pipelined version of the LU decomposition application with respect to the single-threaded version. © 2011 IEEE.

关键词： Application programs

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Toward a cloud architecture for medical imagery grid applications: The Acigna-G project

Toward a cloud architecture for medical imagery grid applica...

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international symposium on Programming and Systems

作者： Benmerar, Tarik Zakaria Boumghar, Fatima Oulebsir Acigna Inc. Algeria ParIMed LRPE USTHB BP32 El Alia Bab-ezzouar Algiers Algeria

ISBN: (纸本)9781457709067

Acigna-G is a new Grid computing platform we propose, for hosting and interacting with GNU/Linux Grid applications through a web portal, without or with a minimal API use. It aims to provide a convenient Cloud Service for Medical Imagery Grid applications. It extends our GIC architecture with an implementation of a light version of the Virtually-distribution parallel Architecture and the Multi-level Services architecture that permit the deployment of distributed Grid applications onto our platform. We propose these architecture as solutions to achieve both the convenience of PaaS Cloud services and the richness of Grid applications. We show how we deploy a MAS segmentation algorithm for Medical Imagery onto our Acigna-G platform. © 2011 IEEE.

关键词： Cloud computing architecture

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Security-driven fault tolerant scheduling algorithm for high dependable distributed real-time system

Security-driven fault tolerant scheduling algorithm for high...

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2011 4th international symposium on parallel Architectures, Algorithms and Programming, PAAP 2011

作者： Ping, Xia Zhou, Xingshe Department of Computer Science Northwestern Polytechnic University Xi'an China

ISBN: (纸本)9780769545752

Critical real time system must run under high dependable environment which guarantees a high level of reliability and security. Fault tolerance and security technique has played an important role in building such environment. In this paper, we provide an improved technique to schedule such tasks with high reliability and security requirement on high dependable distributed real time system. First, the paper analyzed the scheduling problem on high dependable distributed real time system and provided a refined scheduling model which accurately described processors, fault tolerant tasks and security overhead. Based on the scheduling model, it proposed a new and better scheduling algorithm - Security Driven Fault Tolerant Scheduling Algorithm (SDFT) which extended FTRMFF algorithm to tolerate N processors failure at one time, and it introduced a new global scheduler to improve efficiency of scheduling process. Moreover, the SDFT supported flexible security policy applied on real time tasks according to its security requirement and considered the effect of security overhead during scheduling. In addition, the paper adopted and extended the Completion Time Test (CTT) as the schedulability criteria. Simulation experiments showed the SDFT algorithm could achieve better reliability and security at the cost of less number of processors. © 2011 IEEE.

关键词： Real time systems

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