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international symposium on Computer Architecture and High Performance computing (SBAC-PAD)

作者： Claudio Schepke Nicolas Maillard Joerg Schneider Hans-Ulrich Heiss Programa de Pós-Graduação em Computação (PPGC) Instituto de Informática Universidade Federal do Rio Grande do Sul Porto Alegre Brazil Fachgebiet Kommunikations-und Betriebssysteme (KBS) Institut für Telekommunikationssysteme Technische Universität Berlin Berlin Germany

Forecast precisions of climatological models are limited by computing power and time available for the executions. As more and faster processors are used in the computation, the resolution of the mesh adopted to represent the Earth's atmosphere can be increased, and consequently the numerical forecast is more accurate and shows local phenomena. However, a finer mesh resolution, able to include local phenomena in a global atmosphere integration, is still not possible. To overcome this situation, different mesh refinement levels can be used at the same time for different areas. In this context, this paper evaluates how mesh refinement at run time can improve performance for climatological models. In order to contribute with this analysis, an online dynamic mesh refinement was developed. It increases mesh resolution in parts of a parallel distributed model, when special atmosphere conditions are registered during the execution. The results show that the parallel execution of this improvement provides better resolution for the meshes, without a significant increase of execution time.

关键词： Atmospheric modeling Terrestrial atmosphere Computational modeling Meteorology Earth Numerical models

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Two-Stage Tridiagonal Reduction for Dense Symmetric Matrices Using Tile Algorithms on Multicore Architectures

Two-Stage Tridiagonal Reduction for Dense Symmetric Matrices...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Piotr Luszczek Hatem Ltaief Jack Dongarra Innovative Computing Laboratory University of Tennessee Knoxville TN USA

While successful implementations have already been written for one-sided transformations (e.g., QR, LU and Cholesky factorizations) on multicore architecture, getting high performance for two-sided reductions (e.g., Hessenberg, tridiagonal and bidiagonal reductions) is still an open and difficult research problem due to expensive memory-bound operations occurring during the panel factorization. The processor memory speed gap continues to widen, which has even further exacerbated the problem. This paper focuses on an efficient implementation of the tridiagonal reduction, which is the first algorithmic step toward computing the spectral decomposition of a dense symmetric matrix. The original matrix is translated into a tile layout i.e., a high performance data representation, which substantially enhances data locality. Following a two stage approach, the tile matrix is then transformed into band tridiagonal form using compute intensive kernels. The band form is further reduced to the required tridiagonal form using a left-looking bulge chasing technique to reduce memory traffic and memory contention. A dependence translation layer associated with a dynamic runtime system allows for scheduling and overlapping tasks generated from both stages. The obtained tile tridiagonal reduction significantly outperforms the state-of-the art numerical libraries (10X against multithreaded LAPACK with optimized MKL BLAS and 2.5X against the commercial numerical software Intel MKL) from medium to large matrix sizes.

关键词： Tiles Kernel Decision support systems Symmetric matrices Layout Libraries Computer architecture

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I/O-Optimal Distribution Sweeping on Private-Cache Chip Multiprocessors

I/O-Optimal Distribution Sweeping on Private-Cache Chip Mult...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Deepak Ajwani Nodari Sitchinava Norbert Zeh Centre of Unified Computing University College Cork Cork Ireland Madalgo Department of Computer Science University of Aarhus Aarhus Denmark Faculty of Computer Science Dalhousie University Halifax Canada

The parallel external memory (PEM) model has been used as a basis for the design and analysis of a wide range of algorithms for private-cache multi-core architectures. As a tool for developing geometric algorithms in this model, a parallel version of the I/O-efficient distribution sweeping framework was introduced recently, and a number of algorithms for problems on axis-aligned objects were obtained using this framework. The obtained algorithms were efficient but not optimal. In this paper, we improve the framework to obtain algorithms with the optimal I/O complexity of O(sortp(N) + K/PB) for a number of problems on axis aligned objects; P denotes the number of cores/processors, B denotes the number of elements that fit in a cache line, N and K denote the sizes of the input and output, respectively, and sortp(N) denotes the I/O complexity of sorting N items using P processors in the PEM model. To obtain the above improvement, we present a new one-dimensional batched range counting algorithm on a sorted list of ranges and points that achieves an I/O complexity of 0((N + K)/PB), where K is the sum of the counts of all the ranges. The key to achieving efficient load balancing among the processors in this algorithm is a new method to count the output without enumerating it, which might be of independent interest.

关键词： Program processors Complexity theory Multicore processing Compaction Sorting Computational modeling Load management

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Detecting and correcting the index of DAE by the combinatorial relaxation algorithm

Detecting and correcting the index of DAE by the combinatori...

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2011 IEEE 10th international symposium on distributed computing and Applications to Business,Engineering(第十届电子商务、工程及科学领域的分布式计算和应用国际学术研讨会 DCABES 2011)

作者： Xiaolei Zhang Yongxin Yan Xuesong Wu Jianwen Cao International School Beijing University of Posts and Telecommunications Beijing China Laboratory of Parallel Software and ComputationalScience the Institute of SoftwareChinese Academy o Laboratory of Parallel Software and Computational Science the Institute of Software Chinese Academ

The mathematical modeling and simulation based on the Modelica language usually gets a high-index differential-algebraic equation (DAE) system. The structural index reduction algorithms can serve as a fast method to reduce such high-indexed issues. In order to solve the failure of the structural index reduction algorithms in some cases, the combinatorial 1relaxation algorithm is analyzed and studied. Finally, the result of an example shows the combinatorial relaxation algorithm is an effective way to improve the stability of the index reduction algorithms based on the structural index of DAE.

关键词： Modelica differential-algebraic equation index reduction combinatorial relaxation algorithm

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parallelization strategies for ant colony optimisation on GPUs

Parallelization strategies for ant colony optimisation on GP...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jose M. Cecilia Jose M. Garcia Manuel Ujaldon Andy Nisbet Martyn Amos Computer Architecture Department University of Murcia Murcia Spain Computer Architecture Department University of Malaga Malaga Spain Novel Computation Group Division of Computing and IS Manchester Metropolitan University Manchester UK

Ant Colony Optimisation (ACO) is an effective population-based meta-heuristic for the solution of a wide variety of problems. As a population-based algorithm, its computation is intrinsically massively parallel, and it is therefore theoretically well-suited for implementation on Graphics Processing Units (GPUs). The ACO algorithm comprises two main stages: Tour construction and Pheromone update. The former has been previously implemented on the GPU, using a task-based parallelism approach. However, up until now, the latter has always been implemented on the CPU. In this paper, we discuss several parallelisation strategies for both stages of the ACO algorithm on the GPU. We propose an alternative data-based parallelism scheme for Tour construction, which fits better on the GPU architecture. We also describe novel GPU programming strategies for the Pheromone update stage. Our results show a total speed-up exceeding 28x for the Tour construction stage, and 20x for Pheromone update, and suggest that ACO is a potentially fruitful area for future research in the GPU domain.

关键词： Graphics processing unit Instruction sets Kernel parallel processing Algorithm design and analysis Benchmark testing

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Workshop on parallel computing and optimization - PCO

IEEE International Symposium on Parallel and Distributed Pro...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum 2011年 1918-1918页

作者： El Baz, Didier Baker, J. Boukerche, A. Boyer, V. Bouvry, P. Catalyurek, U. Elkihel, M. Frommer, A. Hifi, M. Jourjon, G. Le Cun, B. Leon, C. Phillips, C. Talbi, E. Ucar, B. Watson, J.-P. Team CDA LAAS-CNRS France Kent State University United States University of Ottawa Canada Cirrelt Canada University of Luxembourg Luxembourg Ohio State University United States LAAS-CNRS France Bergische Universität Germany University of Picardie France NICTA Sidney Australia University of Paris 10 France University of La Laguna Spain Sandia National Laboratories United States University of Lille France ENS Lyon France Sandia National Laboratory United States

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Nearest Neighbor Task Allocation for Large-Scale distributed Systems

Nearest Neighbor Task Allocation for Large-Scale Distributed...

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international symposium on Autonomous Decentralized Systems (ISADAS)

作者： Harumasa Tada Faculty of Education Kyoto University of Education Fushimi Kyoto Japan

In this paper, we consider distributed task allocation in distributed systems. In order to improve the performance, using load information of nodes is promising. In reality, however, it is common that load information is not up to date when it is used. Load information may be updated only periodically, or the communication delay for a task to move to other node makes load information out of date. The performance of task allocation schemes is significantly damaged if the load information is old. In order to tackle this problem, we introduce the nearest neighbor approach which is originally proposed for parallel computing. Restricting the communication to between neighboring nodes, the effect of communication delay is suppressed. Simulation results showed that our proposed scheme suppresses the effect of old load information and shows better performance than a previously proposed scheme.

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LACIO: A New Collective I/O Strategy for parallel I/O Systems

LACIO: A New Collective I/O Strategy for Parallel I/O System...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Yong Chen Xian-He Sun Rajeev Thakur Philip C. Roth William D. Gropp Department of Computer Science Texas Tech University Lubbock TX USA Department of Computer Science Illinois Institute of Technology Chicago IL USA Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge TN USA Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA

parallel applications benefit considerably from the rapid advance of processor architectures and the available massive computational capability, but their performance suffers from large latency of I/O accesses. The poor I/O performance has been attributed as a critical cause of the low sustained performance of parallel systems. Collective I/O is widely considered a critical solution that exploits the correlation among I/O accesses from multiple processes of a parallel application and optimizes the I/O performance. However, the conventional collective I/O strategy makes the optimization decision based on the logical file layout to avoid multiple file system calls and does not take the physical data layout into consideration. On the other hand, the physical data layout in fact decides the actual I/O access locality and concurrency. In this study, we propose a new collective I/O strategy that is aware of the underlying physical data layout. We confirm that the new Layout-Aware Collective I/O (LACIO) improves the performance of current parallel I/O systems effectively with the help of noncontiguous file system calls. It holds promise in improving the I/O performance for parallel systems.

关键词： Layout Servers Middleware Optimization Computer science Computer architecture Concurrent computing

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Automated Architecture-Aware Mapping of Streaming Applications Onto GPUs

Automated Architecture-Aware Mapping of Streaming Applicatio...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Andrei Hagiescu Huynh Phung Huynh Weng-Fai Wong Rick Siow Mong Goh School of Computing National University of Singapore Singapore ASTAR-Institute of High Performance Computing Singapore

Graphic Processing Units (GPUs) are made up of many streaming multiprocessors, each consisting of processing cores that interleave the execution of a large number of threads. Groups of threads - called warps and wave fronts, respectively, in nVidia and AMD literature - are selected by the hardware scheduler and executed in lockstep on the available cores. If threads in such a group access the slow off-chip global memory, the entire group has to be stalled, and another group is scheduled instead. The utilization of a given multiprocessor will remain high if there is a sufficient number of alternative thread groups to select from. Many parallel general purpose applications have been efficiently mapped to GPUs. Unfortunately, many stream processing applications exhibit unfavorable data movement patterns and low computation-to-communication ratio that may lead to poor performance. In this paper, we describe an automated compilation flow that maps most stream processing applications onto GPUs by taking into consideration two important architectural features of nVidia GPUs, namely interleaved execution as well as the small amount of shared memory available in each streaming multiprocessors. In particular, we show that using a small number of compute threads such that the memory footprint is reduced, we can achieve high utilization of the GPU cores. Our scheme goes against the conventional wisdom of GPU programming which is to use a large number of homogeneous threads. Instead, it uses a mix of compute and memory access threads, together with a carefully crafted schedule that exploits parallelism in the streaming application, while maximizing the effectiveness of the unique memory hierarchy. We have implemented our scheme in the compiler of the Stream It programming language, and our results show a significant speedup compared to the state-of-the-art solutions.

关键词： Instruction sets Schedules Graphics processing unit Memory management Steady-state Hardware Kernel

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Tracking Structure of Streaming Social Networks

Tracking Structure of Streaming Social Networks

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： David Ediger Jason Riedy David A. Bader Henning Meyerhenke College of Computing Georgia Institute of Technology Atlanta GA USA

Current online social networks are massive and still growing. For example, Face book has over 500 million active users sharing over 30 billion items per month. The scale within these data streams has outstripped traditional graph analysis methods. Real-time monitoring for anomalies may require dynamic analysis rather than repeated static analysis. The massive state behind multiple persistent queries requires shared data structures and flexible representations. We present a framework based on the STINGER data structure that can monitor a global property, connected components, on a graph of 16 million vertices at rates of up to 240,000 updates per second on 32 processors of a Cray XMT. For very large scale-free graphs, our implementation uses novel batching techniques that exploit the scale-free nature of the data and run over three times faster than prior methods. Our framework handles, for the first time, real-world data rates, opening the door to higher-level analytics such as community and anomaly detection.

关键词： Arrays Program processors Facebook Image color analysis Hardware

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