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The MultiCluster model to the integrated use of multiple workstation clusters 1

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15 Workshops Held in Conjunction with the IEEE international parallel and distributed Processing symposium, IPDPS 2000

作者： Barreto, Marcos Ávila, Rafael Navaux, Philippe Institute of Informatics UFRGS Av. Bento Gonçalves 9500 Bl. IV 90501-910 Porto Alegre Brazil

ISBN: (数字)9783540455912

ISBN: (纸本)354067442X

One of the new research tendencies within the well-established cluster computing area is the growing interest in the use of multiple workstation clusters as a single virtual parallel machine, in much the same way as individual workstations are nowadays connected to build a single parallel cluster. In this paper we present an analysis on several aspects concerning the integration of different workstation clusters, such as Myrinet and SCI, and propose our MultiCluster model as an alternative to achieve such integrated architecture. © 2000 Springer-Verlag Berlin Heidelberg.

关键词： Cluster computing

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FedHPM: Online Federated Learning via Heterogeneous Prediction Model 22

FedHPM: Online Federated Learning via Heterogeneous Predicti...

引用

22nd IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2024

作者： Zhang, Zhi Zhang, Shiwen Chen, Shuang Liang, Wei Hunan University of Science and Technology College of Computer Science and Technology Xiangtan China Hunan University of Science and Technology Hunan Key Laboratory for Service Computing and Novel Software Technology School of Computer Science and Engineering Xiangtan411201 China

ISBN: (纸本)9798331509712

In the era of big data and growing privacy concerns, Federated Learning (FL) has emerged as a promising solution for collaborative model training while preserving user data privacy. However, FL faces challenges such as inconsistent data quality and frequent client dropouts, which hinder its performance. To address these challenges, we propose FedHPM, a novel framework that leverages the predictive capabilities of Long Short-Term Memory (LSTM) networks. FedHPM incorporates an intelligent client selection mechanism that utilizes LSTM-based analysis of historical data to forecast clients' potential data quality and dropout likelihood. This mechanism enables efficient selection of the top best-performing clients for participation in each round of global model training. By mitigating the impact of dropouts and optimizing the composition of participating clients, FedHPM significantly improves both the convergence speed and final performance of the global model. Through extensive empirical evaluations, we demonstrate the superior performance of FedHPM in enhancing FL stability, accelerating the convergence rate, and maintaining model accuracy. The results highlight the effectiveness of our framework in addressing the challenges associated with data quality and dropouts, thereby advancing the field of federated learning. © 2024 IEEE.

关键词： Federated learning

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On computation models for clusters of symmetric multiprocessors

On computation models for clusters of symmetric multiprocess...

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international symposium on parallel and distributed Processing (IPDPS)

作者： J. JaJa Institute for Advanced Computer Studies University of Maryland College Park USA

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ST-GCN: A Spatiotemporal Graph Convolution Neural Network for EEG Motor Imagery Signal Decoding 22

ST-GCN: A Spatiotemporal Graph Convolution Neural Network fo...

引用

22nd IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2024

作者： Xu, Jingzhou Qi, Jun Zhang, Junqing Yue, Yong Zhang, Tingting Chen, Jianjun Xi'an Jiaotong-Liverpool University Department of Computing Suzhou China University of Liverpool Department of Electrical Engineering and Electronics Liverpool United Kingdom Fujian Agriculture and Forestry University School of Future Technology Fuzhou China

ISBN: (纸本)9798331509712

Motor imagery (MI) is a mental process extensively used in the experimental paradigm for brain-computer interfaces (BCIs) across various basic science and clinical research studies. Despite its widespread use, accurately decoding intentions from MI poses significant challenges due to the complex nature of brain patterns and the limited sample sizes typically available for machine learning. This paper introduces a Spatiotemporal Graph Neural Network (ST-GCN) designed for MI classification. First, the spatial-temporal convolution layer is used to extract features from raw EEG data, where mixed depthwise convolution extracts temporal features, followed by spatial filtering convolution that decomposes the EEG signal. A graph convolution module employing the max relative aggregator is then utilized to explore the relationships between the spatially decomposed EEG components. In the final step, under the combined supervision of cross-entropy and our proposed channel selection loss, the ST-GCN achieves feature extraction that enhances interclass dispersion and intraclass compactness. We compare ST-GCN with several benchmark EEG decoding methods on two MI datasets: the BCI Competition III Dataset IVa and the BCI Competition IV Dataset 1. ST-GCN outperforms the deep learning benchmark methods by achieving an accuracy of 78.11% and 71.94%, respectively, in 10-fold cross-validation. © 2024 IEEE.

关键词： Graph neural networks

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Overview of RWC massively parallel computer project

Overview of RWC massively parallel computer project

引用

international symposium on High Performance distributed computing

作者： S. Sakai Real World Computing Project Japan

Summary form only given, as follows. The author introduces the massively parallel computer research and development of the Japanese Real World computing Project (RWC). RWC is a ten-year project whose budget is expected to be 600 million to 700 million dollars (US). We plan to develop an original 16 K PE stand-alone computer with a parallel C++ language, a more abstract object-oriented language, and a massively parallel operating system.< >

关键词： Concurrent computing Natural languages Research and development Operating systems

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Adaptive Hybrid FFT: A Novel Pipeline and Memory-Based Architecture for Radix-2k FFT in Large Size Processing 22

Adaptive Hybrid FFT: A Novel Pipeline and Memory-Based Archi...

引用

22nd IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2024

作者： Zhao, Fangyu Xiao, Chunhua Wang, Zhiguo Du, Xiaohua Dong, Bo Chongqing University College of Computer Science Chongqing China Ministry of Education Key Laboratory of Dependable Service Computing in Cyber Physical Society China Sichuan Huacun Zhigu Technology Co. Ltd. Chengdu China

ISBN: (纸本)9798331509712

In the field of digital signal processing, the fast Fourier transform (FFT) is a fundamental algorithm, with its processors being implemented using either the pipelined architecture, well-known for high-throughput applications but weak in hardware utilization, or the memory-based architecture, designed for area-constrained scenarios but failing to meet stringent throughput requirements. Therefore, we propose an adaptive hybrid FFT, which leverages the strengths of both pipelined and memory-based architectures. In this paper, we propose an adaptive hybrid FFT processor that combines the advantages of both architectures, and it has the following features. First, a set of radix-2kmulti-path delay commutators (MDC) units are developed to support high-performance large-size processing. Second, a conflict-free memory access scheme is formulated to ensure a continuous data flow without data contention. Third, We demonstrate the existence of a series of bit-dimension permutations for reordering input data, satisfying the generalized constraints of variable-length, high-radix, and any level of parallelism for wide adaptivity. Furthermore, the proposed FFT processor has been implemented on a field-programmable gate array (FPGA). As a result, the proposed work outperforms conventional memory-based FFT processors by requiring fewer computation cycles. It achieves higher hardware utilization than pipelined FFT architectures, making it suitable for highly demanding applications. © 2024 IEEE.

关键词： Fast Fourier transforms

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kMemvisor: Flexible system wide memory mirroring in virtual environments

kMemvisor: Flexible system wide memory mirroring in virtual ...

引用

22nd ACM international symposium on High-Performance parallel and distributed computing, HPDC 2013

作者： Wang, Bin Qi, Zhengwei Guan, Haibing Dong, Haoliang Sun, Wei Dong, Yaozu Shanghai Key Laboratory of Scalable Computing and Systems Shanghai Jiao Tong University Shanghai China School of Software Shanghai Jiao Tong University Shanghai China Intel China Software Center Shanghai China

ISBN: (纸本)9781450319102

Today's commercial cloud service providers require the availability with an annual uptime percentage at least 99.95%. While memory errors become norms instead of exceptions with the increasing memory's density and capacity in cloud applications. Thus, uncorrected errors from DRAM can be a significant source of system downtime. To address this increasingly important concern, both hardware and software memory mirroring technologies are studied nowadays to provide memory high availability. However, hardware solutions like mirror memory, which uses doubled chip, need dedicated and costly peripheral hardware. While existing software approaches, i.e., virtual machine's checkpoint technology, reduce the expense but incur the high overhead in practical usage. In this paper, we present a novel system called kMemvisor to provide system-wide high availability memory mirroring. It is a software approach achieving flexible multi-granularity memory mirroring via virtualization and binary translation technology. Specifically, kMemvisor first creates backup space of the same size of the specified memory for applications or virtual machines. We can flexibly set memory areas to be mirrored or not mirrored from application level to system-wide. Then, all memory write instructions in the native memory space are captured and instrumented by mirror memory write instructions to synchronize the data in backup space. Furthermore, this instruction level memory synchronization reduces backup overhead and lowers the probability of data loss compared with traditional software approaches. So kMemvisor could use data from the backup space to recover when memory failures happen. The results show that kMemvisor causes 55% overhead in the worst case of system-wide high availability and 30% average for the real world applications, which outperforms the state-of-the-art software approaches even in the worst case. © 2013 ACM.

关键词： Virtual machine

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distributed Formulation of Artificial Reconstruction Technique with Reordering of Critical Data Sets

Distributed Formulation of Artificial Reconstruction Techniq...

引用

international symposium on parallel and distributed computing

作者： Boguslaw Butrylo Marek Tudruj Lukasz Masko Bialystok Technical University Bialystok Poland Polish Japanese Institute of Information Technology Warsaw Poland Institute of Computer Science Polish Academy of Sciences Warsaw Poland

ISBN: (纸本)9780769526381;0769526381

This paper discusses iterative algorithms for reconstruction of 2D images. The formulation of the distributed algorithm and its properties are described. The details of the distributed implementation of the ART (algebraic reconstruction technique) are presented. parallel implementation in a parallel system based on dynamically configurable clusters is proposed

关键词： Image reconstruction Iterative algorithms Sparse matrices Reconstruction algorithms Size measurement Subspace constraints Testing Equations Computer science Information technology

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Message from the EduPar-20 Workshop Chairs

Message from the EduPar-20 Workshop Chairs

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Sushil K Prasad Tia Newhall David Bunde Martina Barnas Satish Puri The University of Texas at San Antonio (Workshop Chair) Swarthmore College (Technical Program Chair) Knox College (Technical Program Vice Chair and Peachy Assignments Chair) Indiana University (Technical Program Panel and Posters Chair) Marquette University (Proceedings Chair)

ISBN: (数字)9781728174457

ISBN: (纸本)9781728174570

Welcome to the NSF/TCPP Workshop on parallel and distributed computing Education (EduPar-20) proceedings. The EduPar-20 workshop, held in conjunction with the IEEE international parallel and computing symposium (IPDPS), is devoted to the development and assessment of educational and curricular innovations and resources for undergraduate and graduate education in parallel and distributed computing (PDC). EduPar brings together individuals from academia, industry, and other educational and research institutes to explore new ideas, challenges, and experiences related to PDC pedagogy and curricula. The workshop is designed in coordination with the IEEE TCPP curriculum initiative on parallel and distributed computing (http://***/~tcpp/curriculum) for computer science and computer engineering undergraduates, and is supported by the NSF and the NSF-supported Center for parallel and distributed computing Curriculum Development and Educational Resources (CDER).

关键词： distributed processing Conferences

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Concurrent specification and timing analysis of digital hardware using SDL

Concurrent specification and timing analysis of digital hard...

引用

15 Workshops Held in Conjunction with the IEEE international parallel and distributed Processing symposium, IPDPS 2000

作者： Turner, Kenneth J. Argul-Marin, F. Javier Laing, Stephen D. Computing Science and Mathematics University of Stirling United Kingdom

ISBN: (纸本)354067442X

Digital hardware is treated as a collection of interacting parallel components. The ANISEED method (Analysis In SDL Enhancing Electronic Design) uses SDL (Specification and Description Language) to specify and analyse timing characteristics of hardware designs. A library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces. © 2000 Springer-Verlag Berlin Heidelberg.

关键词： Specifications

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