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A Dynamic distributed Scheduler for DNN Inference on the Edge

A Dynamic Distributed Scheduler for DNN Inference on the Edg...

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parallel computing and distributed Systems (PCDS), international symposium on

作者： Fei Hu Shivakant Mishra Department of Computer Science University of Colorado Boulder CO USA

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

Edge computing plays a pivotal role in IoT applications that require rapid and secure data processing. How-ever, these applications are typically resource-demanding, and the resources available at the edge are often significantly less than those available in cloud environments. Thus, optimally utilizing these constrained resources is key to fulfilling various application requirements such as low latency, privacy, and cost-effectiveness. Given the dynamic and hybrid characteristics of IoT environments, static scheduling approaches frequently fail to adequately address these complex and varying demands. This paper presents the design, implementation, and evaluation of a dynamic distributed scheduler tailored for DNN inferences on edge computing platforms, based on sophisticated sub-model profiling techniques. This scheduler's core feature is its ability to continuously monitor the state of the IoT infrastructure, dynam-ically adapting the distribution of computing tasks according to real-time environmental and network conditions. Diverging from previous research that typically segments DNN models into two parts, this study proposes a more granular approach that splits models into multiple segments, thereby maximizing the utilization of diverse edge computing resources. The implementation of this scheduler, including integration with a GPU, demonstrates its effectiveness across various DNN models, highlighting its practical utility in leveraging edge computing capabilities.

关键词： Adaptation models Processor scheduling Computational modeling Graphics processing units Prototypes Dynamic scheduling Real-time systems Internet of Things Resource management Edge computing

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RainCloud: Decentralized Coordination and Communication in Heterogeneous IoT Swarms

RainCloud: Decentralized Coordination and Communication in H...

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parallel computing and distributed Systems (PCDS), international symposium on

作者： Filip Loisel Geri Zeqo Andrea Morichetta Anna Lackinger Schahram Dustdar DSG@TU Wien AUXO GmbH Distributed Systems Group TU Wien

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

The increasing volume and complexity of IoT systems demand a transition from the cloud-centric model to a decentralized IoT architecture in the so called computing Continuum, with no or minimal reliance on central servers. This paradigm shift, however, raises novel research concerns for decentralized coordination, calling for accurate policies. However, building such strategies is not trivial. Our work aims to relieve the DevOps engineers from this concern and propose a solution for autonomous, decentralized task allocation at runtime for IoT systems. To this end, we present a semantic communication approach and an ad-hoc lightweight coordination strategy based on Ant Colony Optimization (ACO). We compare the ACO strategy with Random Search and Gossip protocol-based algorithms. We conduct accurate experiments with up to a hundred nodes in both a static and a dynamic environment, i.e., with device outages. We show that ACO finds a matching node with the smallest hops and messages sent. While the Gossip strategy can allocate the most tasks successfully, ACO scales better, thus being a promising candidate for decentralized task coordination in IoT clusters.

关键词： Ant colony optimization Solid modeling Accuracy Runtime Rain Clouds Metaheuristics parallel processing Servers Resource management

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Cybersecurity Insights: Analyzing IoT Data Through Statistical and Visualization Techniques

Cybersecurity Insights: Analyzing IoT Data Through Statistic...

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parallel computing and distributed Systems (PCDS), international symposium on

作者： Jing Li Mohd Shahizan Othman Hewan Chen Lizawati Mi Yusuf Faculty of Computing University Technology Malaysia Johor Bahru Malaysia Research Center of Digital Twins China Jiliang University Hang Zhou China

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

The rising frequency of cyberattacks on Internet of Things (IoT) networks calls for sophisticated approaches to threat analysis and mitigation. The importance of data analysis-especially visualization-in identifying patterns that can guide successful mitigation efforts is emphasized in this research. To address class imbalance issues, we first developed thorough data preparation and basic class analysis. Next, we used the BoT-IoT and TON-IoT datasets to visualize an analysis of 5-tuple network properties. The Spearman and Pearson correlation coefficients were used to statistically validate these properties. Furthermore, class overlapping was revealed using unsupervised techniques using PCA and T-SNE, which shed light on the characteristics of IoT data. Our results show how these visualization methods can help reveal patterns in IoT datasets and illuminate the nature of the representative IoT data, in addition, this approach contributes to the development of robust cybersecurity safeguards for IoT security in the future.

关键词： Correlation coefficient Prevention and mitigation Data visualization distributed databases parallel processing Internet of Things Computer crime Principal component analysis

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RAW 2024 Invited Talk-2: Digital In-Memory computing to Accelerate Deep Learning Inference on the Edge

RAW 2024 Invited Talk-2: Digital In-Memory Computing to Acce...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Stefania Perri University of Calabria

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Deploying Deep Learning (DL) models on edge devices presents several challenges due to the limited setof processing and memory resources, and the bandwidth constraints while ensuring performance and energyrequirements. In-memory computing (IMC) represents an efficient way to accelerate the inference of data-intensiveDL tasks on the edge. Recently, several analog, digital, and mixed digital-analog memory technologies emerged aspromising solutions for IMC. Among them, digital SRAM IMC exhibits a deterministic behavior and compatibilitywith advanced technology scaling rules making it a viable path for integration with hardware accelerators. This workfocuses on discussing the potentially powerful aspects of digital IMC (DIMC) on edge System-on-Chip (SoC) *** limitations and open challenges of DIMC are also discussed.

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Efficient GPU Implementation of Particle Interactions with Cutoff Radius and Few Particles per Cell

Efficient GPU Implementation of Particle Interactions with C...

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parallel computing and distributed Systems (PCDS), international symposium on

作者： David Algis Berenger Bramas Emmanuelle Darles Lilian Aveneau Studio Nyx Université de Poitiers CNRS XLIM Poitiers France Inria Nancy ICube laboratory Illkirch France CNRS XLIM Université de Poitiers Poitiers France

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

This paper presents novel approaches to parallelizing particle interactions on a GPU when there are few particles per cell and the interactions are limited by a cutoff distance. The paper surveys classical algorithms and then introduces two alternatives that aim to utilize shared memory. The first approach copies the particles of a sub-box, while the second approach loads particles in a pencil along the X-axis. The different implementations are compared on three GPU models using Cuda and Hip. The results show that the X-pencil approach can provide a significant speedup but only in very specific cases.

关键词： Surveys Codes Microprocessors Computational modeling Memory management Graphics processing units parallel processing Hip Arithmetic Load modeling

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Application-Agnostic Auto-tuning of Open MPI Collectives using Bayesian Optimization

Application-Agnostic Auto-tuning of Open MPI Collectives usi...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Jeannot, Emmanuel Lemarinier, Pierre Mercier, Guillaume Robert-Hayek, Sophie Sartori, Richard U Bordeaux Labri INRIA Talence France ATOS Echirolles France U Bordeaux INRIA Labri Bordeaux INP Talence France U Lorraine ATOS Echirolles France U Bordeaux Labri INRIA ATOS Echirolles France

ISBN: (纸本)9798350364613;9798350364606

MPI implementations encompass a broad range of parameters that have a significant impact on performance, and these parameters vary based on the specific communication pattern. State-of the art solutions [25], [15] provide a per application tuning of these parameters which require to do the tuning for each application or redo it each time the application changes. Here, we propose an application-agnostic method that leverages Bayesian Optimization, a black-box optimization technique, to discover the optimal parametrization of collective comnunication. We conducted experiments on two HPC platforms, where we tune three Open MN parameters for four distinct collective operations and 18 message sizes. The results of our tuning exhibit an average execution-time improvement up to 48.4% compared to the default parametrization, closely aligning with the tuning achieved through exhaustive sampling. Additionally, our approach drastically reduces the tuning time by 95% in contrast to the exhaustive search, achieving a total search time of merely 6 hours instead of the original 134 hours. Furthermore, we apply our methodology to the NAS benchmarks, demonstrating its efficacy and application agnosticity in real-world scenarios.

关键词： Message Passing Interface High Performance computing Auto-tuning Black-box optimization

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A Converting Autoencoder Toward Low-latency and Energy-efficient DNN Inference at the Edge

A Converting Autoencoder Toward Low-latency and Energy-effic...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Mahmud, Hasanul Kang, Peng Desai, Kevin Lama, Palden Prasad, Sushil K. Univ Texas San Antonio Dept Comp Sci San Antonio TX 78249 USA

ISBN: (纸本)9798350364613;9798350364606

Reducing inference time and energy usage while maintaining prediction accuracy has become a significant concern for deep neural networks (DNN) inference on resourcecon-strained edge devices. To address this problem, we propose a novel approach based on "converting" autoencoder and lightweight DNNs. This improves upon recent work such as early-exiting framework and DNN partitioning. Early-exiting frameworks spend different amounts of computation power for different input data depending upon their complexity. However, they can be inefficient in real-world scenarios that deal with many hard image samples. On the other hand, DNN partitioning algorithms that utilize the computation power of both the cloud and edge devices can be affected by network delays and intermittent connections between the cloud and the edge. We present CBNet, a low-latency and energy-efficient DNN inference framework tailored for edge devices. It utilizes a "converting" autoencoder to efficiently transform hard images into easy ones, which are subsequently processed by a lightweight DNN for inference. To the best of our knowledge, such autoencoder has not been proposed earlier. Our experimental results using three popular image-classification datasets on a Raspberry Pi 4, a Google Cloud instance, and an instance with Nvidia Tesla K80 GPU show that CBNet achieves up to 4.8 x speedup in inference latency and 79% reduction in energy usage compared to competing techniques while maintaining similar or higher accuracy.

关键词： Energy-efficiency Deep Neural Networks Edge computing Early-exit DNNs Converting Autoencoder

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Future computing with the Rogues Gallery

Future Computing with the Rogues Gallery

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Aaron Jezghani Jeffrey Young Will Powell Ronald Rahaman J. Eric Coulter Partnership for an Adv. Comp. Env. Georgia Institute of Technology Atlanta United States School of Computer Science Georgia Institute of Technology Atlanta United States School of Comp. Science and Eng. Georgia Institute of Technology Atlanta United States

The Vertically Integrated Projects (VIP) Program at Georgia Tech provides a multidisciplinary research experience aimed at engaging undergraduate and graduate research students in large-scale computing research projects. Since 2019, the Future computing with the Rogues Gallery VIP course has engaged over 75 students in research on topics related to novel architectures and “post-Moore” computing platforms built around quantum, neuromorphic, near-memory, and reconfigurable *** of the key takeaways from this course for the course designers has been on the correlation between these novel computing platforms and traditional skills, techniques, and tools that are used in the HPC and parallel computing arenas. We discuss these parallels as well as the impacts of this course on general student success and research outcomes.

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Let's Put the Memory Model Front and Center When Teaching parallel Programming in C plus

Let's Put the Memory Model Front and Center When Teaching Pa...

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Dokulil, Jiri Univ Vienna Fac Comp Sci Vienna Austria

ISBN: (纸本)9781665435772

When teaching parallel programming in C++, the memory model is often treated as an afterthought. Even if it is included in the lectures, it may only be covered as an isolated topic near the end of the whole course. We have reorganized the parallel computing course at the University of Vienna to make the memory model an integral part of the course, starting from the very first lecture. Being aware of the memory model and understanding its basic principles helps the students better comprehend parallel programming in C++, even when the memory model is only discussed informally. In the paper, we describe how we integrated the memory model into the course. Based on test results, assignments, and feedback from the students, we consider this approach to be successful.

关键词： education parallel computing memory models

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parallel String Graph Construction and Transitive Reduction for De Novo Genome Assembly 35

Parallel String Graph Construction and Transitive Reduction ...

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Guidi, Giulia Selvitopi, Oguz Ellis, Marquita Oliker, Leonid Yelick, Katherine Buluc, Aydm Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA Lawrence Berkeley Natl Lab Computat Res Div Berkeley CA 94720 USA

ISBN: (纸本)9781665440660

One of the most computationally intensive tasks in computational biology is de novo genome assembly, the decoding of the sequence of an unknown genome from redundant and erroneous short sequences. A common assembly paradigm identifies overlapping sequences, simplifies their layout, and creates consensus. Despite many algorithms developed in the literature, the efficient assembly of large genomes is still an open problem. In this work, we introduce new distributed-memory parallel algorithms for overlap detection and layout simplification steps of de novo genome assembly, and implement them in the diBELLA 2D pipeline. Our distributed memory algorithms for both overlap detection and layout simplification are based on linear-algebra operations over semirings using 2D distributed sparse matrices. Our layout step consists of performing a transitive reduction from the overlap graph to a string graph. We provide a detailed communication analysis of the main stages of our new algorithms. diBELLA 2D achieves near linear scaling with over 80% parallel efficiency for the human genome, reducing the runtime for overlap detection by 1.2-1.3x for the human genome and 1.5-1.9x for *** compared to the state-of-the-art. Our transitive reduction algorithm outperforms an existing distributed-memory implementation by 10.5-13.3x for the human genome and 18-29x for the C. elegans. Our work paves the way for efficient de novo assembly of large genomes using long reads in distributed memory.

关键词： Concurrent computing Runtime Program processors Layout Pipelines Memory management Genomics

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