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Machine Learning for CUDA+MPI Design Rules 36

Machine Learning for CUDA+MPI Design Rules

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36th IEEE international parallel and distributed Processing symposium Workshops, IPDPSW 2022

作者： Pearson, Carl Javeed, Aurya Devine, Karen Sandia National Laboratories AlbuquerqueNM United States

ISBN: (纸本)9781665497473

We present a new strategy for automatically exploring the design space of key CUDA + MPI programs and providing design rules that discriminate slow from fast implementations. In such programs, the order of operations (e.g., G PU kernels, MPI communication) and assignment of operations to resources (e.g., G PU streams) makes the space of possible designs enormous. Systems experts have the task of redesigning and reoptimizing these programs to effectively utilize each new platform. This work provides a prototype tool to reduce that burden. In our approach, a directed acyclic graph of CUDA and MPI operations defines the design space for the program. Monte-Carlo tree search discovers regions of the design space that have large impact on the program's performance. A sequence-to-vector transformation defines features for each explored im-plementation, and each implementation is assigned a class label according to its relative performance. A decision tree is trained on the features and labels to produce design rules for each class;these rules can be used by systems experts to guide their implementations. We demonstrate our strategy using a key kernel from scientific computing - sparse-matrix vector multiplication - on a platform with multiple MPI ranks and GPU streams. © 2022 IEEE.

关键词： parallel programming

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Co-designing the Topology/Algorithm to Accelerate distributed Training 19

Co-designing the Topology/Algorithm to Accelerate Distribute...

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19th IEEE international symposium on parallel and distributed Processing with Applications (IEEE ISPA)

作者： Hou, Xiang Xu, Rui Ma, Sheng Wang, Qiong Jiang, Wei Lu, Hongyi Natl Univ Def Technol Sci & Technol Parallel & Distributed Proc Lab Coll Comp Changsha Peoples R China

ISBN: (纸本)9781665435741

With the development of Deep Learning (DL), Deep Neural Network (DNN) models have become more complex. At the same time, the development of the Internet makes it easy to obtain large data sets for DL training. Large-scale model parameters and training data enhance the level of AI by improving the accuracy of DNN models. But on the other hand, they also present more severe challenges to the hardware training platform because training a large model needs a lot of computing and memory resources that can easily exceed the capacity of a single processor. In this context, integrating more processors on a hierarchical system to conduct distributed training is a direction for the development of training platforms. In distributed training, collective communication operations (including all-to-all, all-reduce, and all-gather) take up a lot of training time, making the interconnection network between computing nodes one of the most critical factors affecting the system performance. The hierarchical torus topology, combined with the Ring All-Reduce collective communication algorithm, is one of the current mainstream distributed interconnection networks. However, we believe that its communication performance is not the best. In this work, we first designed a new intra-package communication topology, i.e. the switch-based fully connected topology, which shortens the time consumed by cross-node communication. Then, considering the characteristics of this topology, we carefully devised more efficient all-reduce and all-gather communication algorithms. Finally, combined with the torus topology, we implemented a novel distributed DL training platform. Compared with the hierarchical torus, our platform improves communication efficiency and provides 1.16-2.68 times speedup in distributed training of DNN models.

关键词： Terms topology hardware training platform distributed training collective communication

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Controlled Copying of Persistent Data Between end Users' SGX Enclaves over an Untrusted Network

Controlled Copying of Persistent Data Between end Users' SGX...

引用

parallel computing and distributed Systems (PCDS), international symposium on

作者： Jun Ishiguro Yasushi Shinjo Akifumi Soyama Department of Computer Science University of Tsukuba Tsukuba Ibaraki Japan

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

It is difficult to protect digital rights while allowing data to be freely copied over the Internet. This paper describes controlled copying of persistent data between two end users's PCs without centralized servers. In the proposed method, a user accesses protected data through the program running in a trusted execution environment (TEE) of the user's PC. When a user sends data to another user, the program in the sender's TEE first encrypts the data and sends it to the program in the receiver's TEE without access permission. Next, the sender's and receiver's programs perform a distributed transaction, and the sender may pass on some of its access rights to the receiver. For example, in the case of data moving, the sender loses access completely and the receiver gains access. In the case of data leasing, the receiver gains access until the end of the lease period, after which the sender is able to access the data again. The proposed method works on an untrusted network, untrusted local persistent storage, and trusted local monotonic counters. Unlike typical digital rights management (DRM) mechanisms, the proposed method enables the resell of data among users while avoiding censorship or privacy violations. The proposed method has been implemented using Intel Software Guard Extensions (SGX). The proposed method can defend against attacks on programs, storage, and networks. Experimental results show that data moving over the Internet could be performed in a useful time.

关键词： Access control Data privacy distributed databases Receivers Permission parallel processing Software Internet Servers Digital rights management

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A Crowdsensing Service Pricing Method in Vehicular Edge computing

A Crowdsensing Service Pricing Method in Vehicular Edge Comp...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Zheng Li Sizhe Tang Hao Tian Haolong Xiang Xiaolong Xu Wanchun Dou State Key Laboratory of Novel Software Technology Nanjing University Nanjing China School of Software Nanjing University of Information Science and Technology Nanjing China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

The rapid advancements in vehicular networking technology have enabled onboard users to access a variety of emerging services like precise navigation and real-time hazard avoidance. However, as the diversity and volume of required data expand and demands intensify, most of vehicular services are unable to satisfy user expectations. Although crowdsensing architectures based on edge computing have been proposed in vehicular networks, how to optimally allocate the sensing service time of roadside units and set appropriate prices for services to maximize user benefits still remain significant challenges. To solve the above issue, in this paper, a crowdsensing service pricing method is proposed in vehicular edge computing. Specifically, a vehicular networking crowdsensing framework based on the edge computing is designed. Then, the optimization problem of perception time pricing during the crowdsensing process is modeled into a Stackelberg game and further the multi-agent deep deterministic policy gradient-based algorithm is employed to obtain the optimal pricing strategy with user profits maximization. Finally, simulation results demonstrate that the proposed method significantly increases the payoff for all participants during the crowdsensing process.

关键词： Crowdsensing Simulation Pricing Games Reinforcement learning Robustness Real-time systems Sensors Vehicle dynamics Edge computing

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Budget-aware Scheduling Algorithm Using Negative Offset Mechanism for Snake Optimization in Heterogeneous Cloud

Budget-aware Scheduling Algorithm Using Negative Offset Mech...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Longxin Zhang Yanfen Zhang Xiaotong Lu Runti Tan Xianming Huang Jianguo Chen College of Computer Science Hunan University of Technology Zhuzhou China School of Software Engineering Sun YatSen University Zhuhai China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Cloud computing, as a cutting-edge computing paradigm, offers substantial data processing and storage capabilities. In a heterogeneous cloud environment, the diversity among cloud platforms results in varying task execution times, posing challenges in minimizing workflow makespan under budget constraints. On this basis, a novel meta-heuristic optimization algorithm, named snake optimizer (SO), is proposed for workflow scheduling in the cloud. Then, a negative offset mechanism is designed to dynamically guide the offset of individual positions during population update to prevent falling into local optimums, thereby optimizing the search for feasible solutions and improving the success rate. Finally, using the negative offset mechanism, a snake optimization budget-aware scheduling algorithm (NO-SO) is developed to schedule budget-constrained workflows in heterogeneous cloud computing environments and minimize the makespan. A series of comparative experiments conducted on real-world scientific workflows demonstrates that the NO-SO algorithm enhances the success rate in finding a feasible solution by 38.89% and 34.45% compared with the advanced MG-PRO algorithm and the original SO algorithm, respectively. Moreover, it achieves an average reduction in makespan of 30.30% and 32.19%.

关键词： Measurement Cloud computing Schedules distributed processing Scheduling algorithms Heuristic algorithms Metaheuristics Optimization methods Scheduling Resource management

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Architecture and Programming of Analog In-Memory-computing Accelerators for Deep Neural Networks

Architecture and Programming of Analog In-Memory-Computing A...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： HsinYu Sidney Tsai IBM

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Deep Neural Networks (DNNs) have demonstrated revolutionary capabilities in AI, such as machine vision, natural language processing, and content generation. However, the growing energy usage due to the excessive amount of data communication between compute and memory units highlights the need to address the “Von Neumann bottleneck.” In-memory computing can achieve high throughput and energy efficiency by computing multiply-accumulate (MAC) operations using Ohm's law and Kirchhoff's current law on arrays of resistive memory devices. In recent years, Analog non-volatile memory (NVM)- based accelerators with energy-efficient, weight-stationary MAC operations in analog NVM memoryarray “Tiles” have been demonstrated in hardware using Phase Change Memory (PCM) devices integrated in the backend of 14-nm CMOS. Based on the hardware demonstrations, we propose a highly heterogeneous and programmable accelerator architecture that takes advantage of a dense and efficient circuit-switched 2D mesh. This flexible architecture can accelerate Transformer, Long-Short-Term- Memory (LSTM), and Convolution Neural Networks (CNNs) while keeping data communication local and massively parallel. We show that by co-optimizing memory devices, DNN algorithms, and specialized digital circuits, competitive end-to-end DNN accuracies can be obtained with the help of hardware-aware training. The author would like to thank all colleagues at IBM Research Almaden, Yorktown, Albany NanoTech, Zurich, and Tokyo for their contributions to this work and the IBM Research AI HW Center.

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Introduction to GraphBLAS 2.0

Introduction to GraphBLAS 2.0

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Brock, Benjamin Buluc, Aydin Mattson, Timothy G. McMillan, Scott Moreira, Jose E. Univ Calif Berkeley EECS Dept Berkeley CA 94720 USA Lawrence Berkeley Natl Lab Computat Res Dept Berkeley CA USA Intel Parallel Comp Labs Ocean Park WA USA Carnegie Mellon Univ Software Engn Inst Pittsburgh PA 15213 USA IBM Thomas J Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9781665435772

The GraphBLAS is a set of basic building blocks for constructing graph algorithms in terms of linear algebra. They are first and foremost defined mathematically with the goal that language bindings will be produced for a wide range of programming languages. We started with the C programming language and over the last four years have produced multiple versions of the GraphBLAS C API specification. In this paper, we describe our next version of the C GraphBLAS specification. It introduces a number of major changes including support for multithreading, import/export functionality, and functions that use the indices of matrix/vector elements. Since some of these changes introduce small backwards compatibility issues, this is a major release we call GraphBLAS 2.0.

关键词： Computer languages distributed processing Multithreading Conferences Collaboration Linear algebra Software

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IDIOMS: Index-powered distributed Object-centric Metadata Search for Scientific Data Management

IDIOMS: Index-powered Distributed Object-centric Metadata Se...

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IEEE/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Wei Zhang Houjun Tang Suren Byna Lawrence Berkeley National Laboratory The Ohio State University

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

Affix-oriented metadata search is one of the essential fuzzy search capabilities that allow users to find data of interest in their voluminous data set with incomplete query conditions. With the recent transition towards object-centric data management systems in the science community, there is a paramount need for the support of such features in distributed settings. However, existing metadata search solutions either do not support efficient affix-oriented metadata search or do not suit well in a distributed setting of object-centric data management systems. To bridge this gap, we introduce IDIOMS, a metadata search solution underpinned by a distributed metadata index, meticulously designed to enable high-performance affix-oriented metadata search for parallel object-centric storage. One of the standout features of IDIOMS is its efficiency in supporting four distinct types of highly demanded metadata queries. Furthermore, IDIOMS is flexibly catering to both independent and collective metadata search operations. Our experimental comparisons with SoMeta, a state-of-the-art metadata query method, demonstrate more than 400× performance boost for independent queries and up to 300× performance improvements for collective queries, while keeping a small index management overhead.

关键词： Bridges Cloud computing distributed databases Metadata Search problems Indexes

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DDoS attack identification based on SDN 20

DDoS attack identification based on SDN

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IEEE 20th international symposium on Network computing and Applications (NCA)

作者： Dobrin, Dobrev Dimiter, Avresky TU Sofia Sofia Bulgaria IRIANC Munich Germany

ISBN: (纸本)9781665495509

The framework that we are proposing is based on Virtual Security Functions (VSF), Openflow, Software Define Network, Mininet, Pox Controller, Virtual Switches. By using Openflow protocol through virtualized environment of SDN, we are able to analyze entire data stream in network environment. By creating DDoS identification virtual security functions, we are capable of increasing the entire network security. VSF will allow for using the capability of this framework in order to protect against different attacks such as DoS, DDoS, MAC address spoofing, NTP amplification attack. All security functions can be activated concurrently, and anomaly detection can be included as well. All functions can run in parallel and based on stream analyses of the Openflow table we can identify anomalies.

关键词： security function botnet distributed denial-of-service attack network function virtualization virtualization openflow flowtable controller

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Compiler-Driven SWAR parallelism for High-Performance Bitboard Algorithms

Compiler-Driven SWAR Parallelism for High-Performance Bitboa...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Florian Fey Sergei Gorlatch University of Muenster Muenster Germany

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

parallel high-performance computing relies on cache-efficient, branch-free algorithms that are often expressed as imperative computations over multidimensional arrays. Numerous problem domains, spanning from image processing to graph analytics, and from state space exploration in combinatorial optimization to computer Chess, require carefully crafted algorithms that capitalize on patterns inherent in the underlying problem structure. A renowned technique, SIMD-Within-A-Register (SWAR), harnesses integer arithmetic to attain significant hardware parallelism. However, this approach typically demands labor-intensive efforts from domain experts with specialized knowledge of the underlying hardware architecture. We therefore present a compiler-driven approach that automates the transformation of conventional array-based C-code into highly tuned integer arithmetic, exploiting SWAR parallelism without the requirement of tedious manual optimization efforts. Our approach achieves substantial performance improvements, exhibiting an average speedup of 30 × compared to conventional array-based implementations.

关键词： Codes Manuals Computer architecture Transforms parallel processing Performance gain Hardware

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