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GraphBLAS: C++ Iterators for Sparse Matrices 36

GraphBLAS: C++ Iterators for Sparse Matrices

引用

36th IEEE international parallel and distributed Processing symposium Workshops, IPDPSW 2022

作者： Brock, Benjamin McMillan, Scott Buluc, Aydin Mattson, Timothy G. Moreira, Jose E. University of California Eecs Department BerkeleyCA United States Software Engineering Institute Carnegie Mellon University PittsburghPA United States Lawrence Berkeley National Laboratory Computational Research Department BerkeleyCA United States Parallel Computing Lab Intel Ocean ParkWA United States Ibm Thomas J. Watson Research Center Yorktown HeightsNY United States

ISBN: (纸本)9781665497473

Iteration over opaque, generic data structures is an important feature of many C++ libraries. Aggressive compiler optimization and inlining enables generic C++ iterators to iterate over complex data structures with performance comparable to that of hand-tuned code with C-language (raw) pointers. In this paper, we describe the sparse matrix iterators in the current draft of the C++ GraphBLAS API, their support for a variety of backend data formats, and implementation strategies we have considered. We compare performance of these iterators to that of hand-tuned iteration with raw pointers, showing that our iterators introduce minimal overhead. We consider extensions to our iterator design for interoperability with the draft C++ Graph Library proposal and to support different semantics for iterating over sparse matrices (by row, by column, by specific diagonals, etc.). © 2022 IEEE.

关键词： Semantics

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Plaster: an Embedded FPGA-based Cluster Orchestrator for Accelerated distributed Algorithms

Plaster: an Embedded FPGA-based Cluster Orchestrator for Acc...

引用

35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Farinelli, Lorenzo De Vincenti, Daniele Valentino Damiani, Andrea Stornaiuolo, Luca Brondolin, Rolando Santambrogio, Marco D. Sciuto, Donatella Politecn Milan Dipartimento Elettron Informaz & Bioingn DEIB Milan Italy

ISBN: (纸本)9781665435772

The increasing use of real-time data-intensive applications and the growing interest in Heterogeneous Architectures have led to the need for increasingly complex embedded computing systems. An example of this is the research carried out by both the scientific community and companies toward embedded multi-FPGA systems for the implementation of the inference phase of Convolutional Neural Networks. In this paper, we focus on optimizing the management system of these embedded FPGA-based distributed systems. We extend the state-of-the-art FARD framework to data-intensive applications in an embedded scenario. Our orchestration and management infrastructure benefits from compiled language and is accessible to end-users by the means of Python APIs, which provides a simple way to interact with the cluster and design apps to run on the embedded nodes. The proposed prototype system consists of a PYNQ-based cluster of multiple FPGAs and has been evaluated by running an FPGA-based You Only Look Once (YOLO) image classification algorithm.

关键词： multi-FPGAs Cluster Orchestrator Embedded

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Towards Accelerating k-NN with MPI and Near-Memory Processing

Towards Accelerating k-NN with MPI and Near-Memory Processin...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Hooyoung Ahn Seonyoung Kim Yoomi Park Woojong Han Nick Contini Bharath Ramesh Mustafa Abduljabbar Dhabaleswar K. Panda Supercomputing Technology Research Center Electronics and Telecommunications Research Institute Department of Computer Science and Engineering The Ohio State University

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Message Passing Interface (MPI) is a common parallel programming model in High-Performance computing fields. Recently, it has been widely used in Artificial Intelligence (AI) applications. However, the performance of those applications is limited by the memory wall problem, which is the performance gap between the processor and memory. To address these problems, we propose a novel computing architecture for accelerating k-NN query, which is the key operation of AI applications. The proposed computing architecture involves two or more computing nodes within a rack using the memory of an NMP device as a communication buffer and the accelerator of the NMP device for MPI collective communication. The superiority of the proposed method is that it reduces data copying during local computation and eliminates the network cost of gathering local computation results for global computation. Furthermore, it can enhance performance by processing data in the device's memory through near-memory processing. However, since these NMP devices are still in development, with no commercially available products currently, we have undertaken the task of developing them ourselves. Despite these circumstances, to demonstrate the feasibility of our proposed approach, we have implemented it in a single-node environment without making any unreasonable assumptions and have compared it with conventional approaches. Although we are using a single-node environment, we have designed a more sophisticated architecture, analyzed the time complexity, and compared the estimated performance of both the conventional and proposed approaches. We can conclude that the proposed computing architecture is feasible, and we anticipate an even more performance enhancement in a multi-node environment.

关键词： Performance evaluation Costs parallel programming Message passing High performance computing Conferences Computer architecture

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CAA: A Concurrent AA Tree via Logical ordering

CAA: A Concurrent AA Tree via Logical ordering

引用

international symposium on parallel and distributed computing

作者： Kapil Kumar Attinagaramu Praveen Alapati Computer Science Engineering Department (Super computer lab) École Centrale School of Engineering Mahindra University Hyderaba India

ISBN: (数字)9798350369199

ISBN: (纸本)9798350369205

Efficient implementation of concurrent data structures is crucial for ensuring safe and efficient access to data in shared-memory environments. Maintaining height balance within these concurrent structures in a multi-core setting is vital to prevent performance degradation or structural imbalances. Self-balancing trees play a key role in achieving consistent performance across various workloads, ensuring operations have logarithmic time complexity. This paper presents a concurrent implementation of the AA Tree using logical ordering, employing lazy synchronization to harmonize threads that perform concurrent operations on the shared AA tree. The paper discusses concurrent algorithm design for basic operations (insert(), remove(), and contains()) on the AA tree. We extensively analyze the CAA tree’s performance compared to state-of-the-art implementations across various workloads. Our CAA Tree implementation scales well with the number of threads and achieves an average speedup of $46.4 x$ over the sequential implementation when using 96 threads. Compared to concurrent implementations of AVL trees [2], Red-Black trees [3], Treaps [4], and Contention Adapting Search trees trees [5], the speedup is $2.1 \mathrm{x}, 1.6 \mathrm{x}, 1.6 \mathrm{x}$, and 1.1 x, respectively.

关键词： Degradation Energy consumption distributed databases Vegetation Data structures Safety Synchronization Time complexity

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Accelerating Lossy and Lossless Compression on Emerging BlueField DPU Architectures

Accelerating Lossy and Lossless Compression on Emerging Blue...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Yuke Li Arjun Kashyap Weicong Chen Yanfei Guo Xiaoyi Lu University of California Merced Merced CA USA Argonne National Laboratory Lemont IL USA

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Data compression has become a crucial technique in addressing performance bottlenecks caused by increasing data volumes in High-Performance computing (HPC), Big Data, and Deep Learning (DL). Despite its potential to boost system performance, recent studies have identified significant challenges with existing compression methods, mainly due to their high computational demands amidst continuously growing data sizes. Concurrently, the advent of Data Processing Units (DPUs), equipped with programmable System-on-Chip (SoC) and specialized compression accelerators, offers a promising opportunity to alter the landscape of data compression. This paper explores the complexities and potential of leveraging NVIDIA BlueField DPUs to accelerate lossy and lossless compression. Towards this, we introduce PEDAL, an innovative library that leverages the hardware capabilities of DPUs to unify and optimize data compression designs. Moreover, we seamlessly co-design PEDAL with the popular MPICH MPI library, demonstrating up to 101x speedup in compression time and 88x decrease in communication latency. Drawing on these achievements, we share our experience with various research communities about accelerating data compression on DPUs in communication-oriented HPC scenarios.

关键词： Deep learning distributed processing System performance High performance computing Data compression Computer architecture Data processing

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distributed Sparse Random Projection Trees for Constructing K-Nearest Neighbor Graphs

Distributed Sparse Random Projection Trees for Constructing ...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Isuru Ranawaka Md Khaledur Rahman Ariful Azad Indiana University Bloomington IN USA Meta Inc.

A random projection tree that partitions data points by projecting them onto random vectors is widely used for approximate nearest neighbor search in high-dimensional space. We consider a particular case of random projection trees for constructing a k-nearest neighbor graph (KNNG) from high-dimensional data. We develop a distributed-memory Random Projection Tree (DRPT) algorithm for constructing sparse random projection trees and then running a query on the forest to create the KNN graph. DRPT uses sparse matrix operations and a communication reduction scheme to scale KNN graph constructions to thousands of processes on a supercomputer. The accuracy of DRPT is comparable to state-of-the-art methods for approximate nearest neighbor search, while it runs two orders of magnitude faster than its peers. DRPT is available at https://***/HipGraph/DRPT.

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A Scheduling Algorithm for Hyperledger Fabric Based on Transaction Batch Processing

A Scheduling Algorithm for Hyperledger Fabric Based on Trans...

引用

international symposium on parallel and distributed computing

作者： Junyu Jia Ou Wu Shanshan Li Rufei Ma He Zhang Anhui Normal University China State Key Laboratory of Novel Software Technology Nanjing University China Software Institute Nanjing University China Department of Basic Courses The PLA Army Engineering University

ISBN: (数字)9798350369199

ISBN: (纸本)9798350369205

Hyperledger Fabric (Fabric for short), is a consortium blockchain platform that adopts the smart contract paradigm and provides complete operational functions. Although it has become the system with the highest throughput among open source blockchain systems, its performance cannot meet the needs of industrial-grade application scenarios. To further expand the application scenarios of blockchain, this paper proposes a Transaction Batch Processing Scheduling (TBPS) algorithm for multi-channel Fabric networks based on Lyapunov optimization theory. The algorithm maximizes the consensus efficiency of the system while ensuring the minimum transaction accumulation, and provides stability conditions and optimal performance for the system under transaction batch processing. Finally, we built a blockchain network of Fabric’s latest stable version v 2.0 via the cloud platform, providing an order of magnitude of algorithmic parameters by testing transaction processing rates. To simulate the distribution of performance indicators such as transaction delay, system transaction accumulation and average transaction processing rate under different impact factors, and verify the effectiveness of the proposed TBPS algorithm.

关键词： distributed ledger Batch production systems Throughput Fabrics Stability analysis Blockchains Classification algorithms Thermal stability Optimization Testing

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Interactive Data Visualization to Optimize Decision-Making Process

Interactive Data Visualization to Optimize Decision-Making P...

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parallel computing and distributed Systems (PCDS), international symposium on

作者： Zheng-Bin Phang Su-Cheng Haw Tong-Ern Tai Kok-Why Ng Faculty of Computing and Informatics Multimedia University Cyberjaya Malaysia

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

The increasing volume and complexity of data in today's business environment present significant challenges for traditional data analysis methods. Static reports and spreadsheets often fall short in providing comprehensive insights necessary for strategic decision-making. This paper addresses the critical issue of enhancing data comprehension and utilization through interactive data visualization. The primary objectives of this paper are to explore various visualization techniques, design and implement an interactive dashboard with a content-based recommender system, and evaluate its effectiveness in optimizing business processes. The content-based recommender system utilizes TF-IDF vectorization and cosine similarity to offer personalized product recommendations. The process includes data cleaning, preprocessing, and integrating the recommender system into the dashboard. Comprehensive evaluation through user testing and performance analysis ensures the vizualisations and recommender system's accuracy, responsiveness, and effectiveness. In addition, by leveraging descriptive analytics, the paper aims to create a user-friendly tool to explore data, uncover hidden patterns, and facilitate decision-making. The expected outcome of this paper is an interactive dashboard that significantly enhances data comprehension and strategic decision-making for businesses.

关键词： Accuracy Decision making Data visualization Prediction algorithms Real-time systems Performance analysis Predictive analytics Recommender systems Business Testing

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DiFlip: Directed Flip-Chain Operation for Regular Directed Graph

DiFlip: Directed Flip-Chain Operation for Regular Directed G...

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parallel computing and distributed Systems (PCDS), international symposium on

作者： Saptadi Nugroho Christian Schindelhauer Albert Ludwigs Universität Freiburg Freiburg Germany

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

We introduce the directed Flip-Chain algorithm, which transforms the regular directed graph into another regular directed graph by swapping two adjacent vertices in the trail of directed edges. Repeatedly applying the directed Flip-Chain operation to an arbitrary regular directed graph will build every regular directed graph with the same probability in the limit. The directed Flip-Chain algorithm preserves the connectivity and regularity of a regular directed graph. The operations of the directed Flip-Chain will transform any regular directed graph into an expander and introduce randomness to the regular directed graph, which is particularly useful in dynamic graphs. Cheeger's inequality determines whether a directed graph is an expander-directed graph. The simulation results indicate that the directed vertex expansion and the directed edge conductance of regular directed graphs converge after performing directed Flip-Chain operations. In addition, the directed Flip-Chain operation with the Push-Sum communication protocol algorithm for randomized rumor spreading on a regular directed graph is observed. The simulation results indicate that the Push-Sum protocol algorithm with directed Flip-Chain operations improves the Mean Squared Error compared to the Push-Sum protocol algorithm without Flip-Chain operations regarding time complexity for rumor dissemination.

关键词： Protocols Network topology Simulation Heuristic algorithms Directed graphs Transforms parallel processing Topology Time complexity

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Design and Development of XiveNet: A Hybrid CAN Research Testbed

Design and Development of XiveNet: A Hybrid CAN Research Tes...

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international symposium on parallel and distributed computing

作者： William Luke Lambert Sheikh Ghafoor Haley Burnell Brennan Huber Farah Kandah Anthony Skjellum Tennessee Technological University Auburn University

ISBN: (数字)9798350369199

ISBN: (纸本)9798350369205

We have developed an affordable distributed Internet of Things (IoT) testbed, named XiveNet, to conduct in-vehicle security research. This testbed merges the adaptability of simulators with the real-time ECU characteristics of actual vehicles. The testbed is made up of ECU chips found in vehicles, Raspberry Pis, and is combined with a bus master simulator. Our experiments with CAN (controller area network) traffic from actual vehicles (Oak Ridge National Laboratories Road Data Set) demonstrate that our testbed closely replicates the attributes of a real vehicle. We have further authenticated our testbed by deploying SecCAN, a secure CAN algorithm, and evaluating its security by injecting invalid frames. Furthermore, we examined ORNL’s timing-based intrusion detection on our testbed and successfully produced alerts. Additionally, we incorporated Named Data Networking (NDN) capable nodes, providing researchers with an additional resource to develop future in-vehicle security solutions. Finally, we have proposed a bitrate hopping technique focused on preventing the denial of service attack and conducted a preliminary investigation using the testbed. Our evaluation and validation indicate that the testbed provides the real-world vehicle environment with the flexibility of a simulation environment that supports a wide range of hardware and software configurations.

关键词： Roads Prevention and mitigation Laboratories Intrusion detection distributed databases Software Real-time systems Hardware Security Internet of Things

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