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Multi-Core Multi-Rule VeBPF Firewall for Secure FPGA IoT Device Deployments

Multi-Core Multi-Rule VeBPF Firewall for Secure FPGA IoT Dev...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Zaid Tahir Sahan Bandara Martin Herbordt ECE Department CAAD Lab Boston University USA

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

FPGAs are often deployed in IoT devices: sensor technology is advancing rapidly and microcontrollers may be unable to handle the needed throughput. But with their connections to the internet and only basic system support, IoT devices may be easy targets of cyberattacks. Current FPGA-based SmartNIC defenses against cyberattacks, however, are mostly applicable in cloud deployments. In order to mitigate cyberattacks on resource-limited IoT devices, we have developed a multi-core multi-rule VeBPF (Verilog extended Berkeley Packet Filter) firewall for FPGA-based IoT devices. This VeBPF firewall accepts standard eBPF bytecode as firewall rules; these rules are run by VeBPF CPU cores. Any number of VeBPF cores can be generated by specifying the N VeBPF parameter.

关键词： Firewalls (computing) Multicore processing Microcontrollers Throughput Information filters Systems support Internet of Things

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Dynamic Resource Management for Cloud-native Bulk Synchronous parallel Applications

Dynamic Resource Management for Cloud-native Bulk Synchronou...

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international symposium on Object-Oriented Real-Time distributed computing

作者： Evan Wang Yogesh Barve Aniruddha Gokhale Hongyang Sun Dept of CS Vanderbilt University Nashville TN USA Dept of EECS University of Kansas Lawrence KS USA

Many traditional high-performance computing applications including those that follow the Bulk Synchronous parallel (BSP) communication paradigm are increasingly being deployed in cloud-native virtualized and multi-tenant container clusters. However, such a shared, virtualized platform limits the degree of control that BSP applications can have in effectively allocating resources. This can adversely impact their performance, particularly when stragglers manifest in individual BSP supersteps. Existing BSP resource management solutions assume the same execution time for individual tasks at every superstep, which is not always the case. To address these limitations, we present a dynamic resource management middleware for cloud-native BSP applications comprising a heuristics algorithm that determines effective resource configurations across multiple supersteps while considering dynamic workloads per superstep, and trading off performance improvements with reconfiguration costs. Moreover, we design dynamic programming and reinforcement learning approaches that can be used as pluggable strategies to determine whether and when to enforce a reconfiguration. Empirical evaluations of our solution show between 10% and 25% improvement in performance over a baseline static approach even in the presence of reconfiguration penalty.

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State-Space Search to Find Energy-Aware Pareto-Efficient Optimal Task Schedules

State-Space Search to Find Energy-Aware Pareto-Efficient Opt...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Yasith Udagedara Andrea Raith Oliver Sinnen Department of Electrical Computer and Software Engineering University of Auckland New Zealand Department of Engineering Science University of Auckland New Zealand

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Bi-objective scheduling for parallel computing, in particular with the objectives to minimize makespan and energy, has been well studied in the literature. Numerous works have proposed algorithms that use Dynamic Voltage and Frequency Scaling (DVFS) as the mechanism to reduce energy consumption. Given the NP-hard nature of the combinatorial task scheduling problem, these algorithms are mostly heuristics, producing only a single or few schedules for a given instance. This research explores bi-objective task scheduling with the goal to find the set of Pareto-efficient solutions for a given small instance, using DVFS to balance energy and performance. We undertake this using a branch-and-bound depth-first search within an allocation-ordering state space model. Varying scaling factors and static energy models are considered. The proposed approach is evaluated with a dataset of small graphs resulting in thousands of produced schedules. In contrast to heuristics, our approach computes numerous trade-off solutions for a given problem instance as a Pareto-efficient set.

关键词： Schedules Energy consumption Processor scheduling Heuristic algorithms Computational modeling Voltage parallel processing

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Autonomous Mobile Robots: Refining the Computational Landscape

Autonomous Mobile Robots: Refining the Computational Landsca...

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Buchin, Kevin Flocchini, Paola Kostitsyna, Irina Peters, Tom Santoro, Nicola Wada, Koichi TU Eindhoven Dept Math & Comp Sci Eindhoven Netherlands Univ Ottawa EECS Ottawa ON Canada Carleton Univ Sch Comp Sci Ottawa ON Canada Hosei Univ Fac Sci & Engn Tokyo Japan

ISBN: (纸本)9781665435772

Within distributed computing, the study of distributed systems of identical mobile computational entities, called robots, operating in a Euclidean space is rather extensive. When a robot is activated, it executes a Look-Compute-Move cycle: it takes a snapshot of the environment (Look);with this input, it computes its destination (Compute);and then it moves towards that destination (Move). The choice of the times a robot is activated and how long its cycle lasts is made by a fair (but adversarial) scheduler;three schedulers are usually considered: fully synchronous (FSYNC), semi-synchronous (SSYNC), and asynchronous (ASYNC). Extensive investigations have been carried out, under all those schedulers, within four models, corresponding to different levels of computational and communication powers of the robots: OBLOT (the weakest), LUMI (the strongest), and two intermediate models FSTA and FCOM. The many results for specific problems have provided insights on the relationships between the models and with respect to the activation schedulers. Recently, a comprehensive characterization of these relationships has been provided with respect to the FSYNC and SSYNC schedulers;however, in several cases, the results were obtained under some restrictive assumptions (chirality and/or rigidity). In this paper, we improve the characterization by removing those assumptions, providing a refined map of the computational landscape for those robots. We also establish some preliminary results with respect to the ASYNC scheduler.

关键词： mobile robots oblivious persistent memory finite communication finite-state distributed computing

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Modeling Multi-Threaded Aggregated I/O for Asynchronous Checkpointing on HPC Systems

Modeling Multi-Threaded Aggregated I/O for Asynchronous Chec...

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international symposium on parallel and distributed computing

作者： Mikaila J. Gossman Bogdan Nicolae Jon C. Calhoun Holcombe Department of Electrical and Computing Engineering Clemson University Clemson SC Mathematics and Computer Science Division Argonne National Laboratory Lemont IL

HPC systems encompass more components with each new generation. As a result, the process of interacting with stable storage systems like parallel file systems (PFS) becomes increasingly difficult. Larger systems often result in more frequent failures, increasing the need and frequency to incorporate fault-tolerant mechanisms. One example is checkpoint-restart (C/R), where applications or systems save their data to non-volatile storage devices, such as a PFS. On failure, the system or application is restored to a saved state and computation continues. Today, asynchronous C/R is gaining traction for its ability to checkpoint data to permanent storage concurrently with the application. However, asynchronous C/R brings about many new challenges. For starters, asynchronous C/R introduces complex resource contention between the application and the C/R implementation. Additionally, some implementations adopt file-per-process writing strategies, which overwhelm PFS’ at high core counts. In this work, we explore how multi-threaded POSIX I/O impacts aggregated throughput. To this extent we characterize the influence of different I/O parameters, such as the number of writer threads and how they access storage devices, has on aggregated I/O. We use the information gathered in this study to identify best practices when performing aggregated I/O as a first step in designing an efficient I/O aggregation scheme for asynchronous C/R.

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Noise-Resilient Empirical Performance Modeling with Deep Neural Networks 35

Noise-Resilient Empirical Performance Modeling with Deep Neu...

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Ritter, Marcus Geiss, Alexander Wehrstein, Johannes Calotoiu, Alexandru Reimann, Thorsten Hoefler, Torsten Wolf, Felix Tech Univ Darmstadt Dept Comp Sci Darmstadt Germany Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9781665440660

Empirical performance modeling is a proven instrument to analyze the scaling behavior of HPC applications. Using a set of smaller-scale experiments, it can provide important insights into application behavior at larger scales. Extra-P is an empirical modeling tool that applies linear regression to automatically generate human-readable performance models. Similar to other regression-based modeling techniques, the accuracy of the models created by Extra-I' decreases as the amount of noise in the underlying data increases. This is why the performance variability observed in many contemporary systems can become a serious challenge. In this paper, we introduce a novel adaptive modeling approach that makes Extra-P more noise resilient, exploiting the ability of deep neural networks to discover the effects of numerical parameters, such as the number of processes or the problem size, on performance when dealing with noisy measurements. Using synthetic analysis and data from three different case studies, we demonstrate that our solution improves the model accuracy at high noise levels by up to 25% while increasing their predictive power by about 15%.

关键词： Performance analysis performance modeling deep learning artificial neural networks high performance computing parallel processing

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High Performance Streaming Tensor Decomposition 35

High Performance Streaming Tensor Decomposition

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Soh, Yongseok Flick, Patrick Liu, Xing Smith, Shaden Checconi, Fabio Petrini, Fabrizio Choi, Jee Univ Oregon Comp & Info Sci Eugene OR 97403 USA Google Mountain View CA 94043 USA Facebook Cambridge MA USA Microsoft Redmond WA USA Intel Parallel Comp Lab Santa Clara CA USA

ISBN: (纸本)9781665440660

We present a new algorithm for computing tensor decomposition on streaming data that achieves up to 102x speedup over the stale-of-the-art CP-stream algorithm through lower computational complexity and performance optimization. For each streaming lime slice, our algorithm partitions the factor matrix rows into those with and without updates and keeps them in Gram matrix form to significantly reduce the required computation. We also improve the scalability and performance of the matricized tensor times Khatri-Rao product (MTTKRP) kernel, a key performance bottleneck in many tensor decomposition algorithms, by reducing the synchronization overhead through the combined use of mutex locks and thread-local memory. For problems with constraints (e.g., non-negativity), we apply data blocking and operation fusion to the alternating direction method of multiplier (ADMM) kernel in the constrained CP-stream algorithm. By combining this ADMM optimization with the aforementioned MTTKRP optimization, our improved algorithm achieves up to 47x speedup over the original. We evaluate the performance and scalability of our new algorithm and optimization techniques using a 56-core quad-socket Intel Xeon system on four representative real-world tensors.

关键词： tensor decomposition streaming high performance algorithm

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An Architecture-Agnostic Dataflow Mapping Framework on CGRA

An Architecture-Agnostic Dataflow Mapping Framework on CGRA

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jiangnan Li Yazhou Yan Jingyuan Li Shaoyang Sun Boyin Jin Wenbo Yin Lingli Wang State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Coarse-Grained Reconfigurable Arrays (CGRAs) are promising accelerators in the rapidly evolving field of high-performance computing (HPC). However, their potential is limited by the inability of compilers to efficiently map complex application kernels to architectures. In this paper, we propose an architecture-agnostic mapping framework called AGILE, which has a loosely coupled flow that contains architecture modeling and dataflow intermediate representation (IR) generation, hierarchical mapping and design space exploration (DSE). We extend mapping to end-to-end flow for better evaluation of architectures, flexible modeling and IR allow for adapting to and exploring various architectures, and hierarchical dataflow mapping methodology enables better evaluation of proposed architectures. The experiments show that our partitioning algorithm adapts to large-scale DFGs, and divide-and-conquer reduces the problem size. Our framework achieves a 1.86 × and 1.4 × improvement in throughput over the baseline CGRA when compared to CGRA-ME and LISA, respectively, and offers significant mapping acceleration, being 133 × and 33.3 × faster. On the Hycube architecture, we improve utilization and throughput by 4× compared to Morpher. Moreover, the DSE of a range of architectures demonstrates the effectiveness of our approach.

关键词： Adaptation models distributed processing Power demand High performance computing Scalability Computer architecture Throughput

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QDL: Quantitative Dynamic Latency Model in Permissioned Blockchain System

QDL: Quantitative Dynamic Latency Model in Permissioned Bloc...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Jiacheng Wei Qingmei Wang Zheng Wang School of Artificial Intelligence Beihang University Beijing Beijing Advanced Innovation Center for Future Blockchain and Privacy Computing Beihang University Beijing National Center for Materials Service Safety University of Science and Technology Beijing Beijing Institute of Cyber Science and Technology Shanghai Jiao Tong University Shanghai Key Laboratory of Integrated Administration Technologies for Information Security

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Latency, as a critical attribute influencing scalability and consistency in blockchain systems, has attracted significant research attention. This paper addresses the issue of latency evaluation by presenting a novel framework. We thoroughly analyze the factors affecting latency in blockchain system, including concurrency, consistency, and contention. To accurately model the correlation between latency and the quantity of nodes in permissioned blockchain setup, we introduce the Latency Regression Loss (LRL) function. By utilizing Newton’s interpolation and least squares methods, we determine the hyperparameters. Subsequently, we devise the framework for the Quantitative Dynamic Latency (QDL) evaluation model, which accounts for both the growth rate and magnitude of latency. Utilizing the parameters derived from the LRL function facilitated the calculation of latency growth rate, allowing for a comprehensive evaluation of latency. Finally, we validated the accuracy of the LRL function through extensive experiments and simulated the adaptability of the QDL model in latency assessment.

关键词： Concurrent computing Adaptation models Interpolation distributed processing Protocols Scalability Evaluation models Mathematical models Blockchains Least mean squares methods

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Invited Paper: On the Cost-Optimal parallel Solution of the Majority Problem

Invited Paper: On the Cost-Optimal Parallel Solution of the ...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jie Wu Center for Networked Computing Temple University USA

The majority problem can be stated as follows: there is a collection of n bank cards that belong to different bank accounts. The only way to “read” these cards is through one or more two-input “equivalence testers”. Each tester accepts two cards and outputs “yes” if two input cards correspond to the same bank account or “no” if they do not. The objective of the majority problem is to design a solution that uses the minimum number of tests to determine if more than $n/2$ cards belong to the same bank account and then find these cards. We first review two sequential solutions, including the Boyer-Moore optimal linear solution (i.e., with a time complexity of $O(n))$. Then, we introduce an optimal elimination solution together with a special structure to support a cost-optimal parallel solution that solves the problem in $O(\log n)$ using $O(n/ \log n)$ processors (i.e., testers). That is, this solution matches the optimal sequential solution with $O(n)$ operations.

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