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FHNTT: a flexible Number Theoretic Transform design based on hybrid-radix butterfly

FHNTT: a flexible Number Theoretic Transform design based on...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Li Li Rengang Li Yaqian Zhao Ruyang Li Zhiyuan Su Xuelei Li IEIT SYSTEMS Co. Ltd Jinan China Inspur (Beijing) Electronic Information Industry Co. Ltd Beijing China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Emerging technologies, such as cloud computing and artificial intelligence, significantly arouse concern about data security and privacy. Homomorphic encryption (HE) is a promising invention, which enables computation on encrypted data without decrypting it so as to ensure data security and privacy. Nevertheless, computation within homomorphic encryption involves time-consuming operations, e.g., Number Theoretic Transform (NTT). The tremendous computation overhead is the critical obstacle in deploying HE applications widely. Besides, in order to meet the performance and security requirements of different applications, it is pivotal to design parametric NTT architecture. In this paper, we propose a flexible and parametric NTT accelerating scheme based on hybrid-radix butterfly, named FHNTT. Specifically, we construct high radix butterfly units and divide the computation of them into several stages such that every stage can be performed pipelined. The number of required twiddle factors declines with the increase of radix value. In addition, we adopt address offset strategy to reduce memory consumption. We implement FHNTT on FPGA due to its fine-grained parallel computing capabilities and customized architecture. Empirical results show that FHNTT has an improved performance compared with other NTT architectures and supports a wide range of parameters. Concretely, FHNTT achieves up to 1.99 × to 2.78 × improvement in latency over other FPGA implementations and the memory utilization rate is up to 94%. Moreover, the flexibility makes FHNTT applicable to multiple use cases.

关键词： Hands Data privacy Technological innovation distributed processing Memory management Transforms parallel processing System-on-chip Homomorphic encryption Field programmable gate arrays

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Towards Fine-Grained parallelism in parallel and distributed Python Libraries

Towards Fine-Grained Parallelism in Parallel and Distributed...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jamison Kerney Ioan Raicu John Raicu Kyle Chard College of Computing Illinois Institute of Technology Chicago Illinois Department of Computer Science University of Chicago Chicago Illinois

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

There is a growing need, for example in machine learning and analytics, to decompose applications into smaller schedulable units. Such decomposition can improve performance, reduce energy consumption, and increase resource utilization. Unfortunately, enabling fine-grained parallelism comes with significant overheads and requires improvements at all layers of the programming stack. We consider the challenges of supporting fine-grained parallelism in the increasingly popular Python-based programming libraries. Specifically, we focus on Parsl, a Python library that is widely used to parallelize the execution of fine-grained Python functions. Parsl's Python-based runtime supports a maximum throughput of around 1200 tasks per second—insufficient to meet modern application needs. We perform a comprehensive analysis of Parsl and identify areas that prohibit it from achieving higher throughput. We first profile Parsl components and identify that, with fine-grained tasks workers are often not saturated. We find that tasks spend a majority of their time in the components between the scheduler and worker, however, we also learned that the scheduler is capable of submitting thousands of tasks per second. We then focused on developing new optimizations and implementing crucial components in C to improve throughput. Our new implementation increases Parsl's throughput 6 fold.

关键词： Runtime Machine learning parallel processing Programming Throughput Libraries Resource management

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AutoMP: A Tool to Automate Performance Testing for Model Placement on GPUs

AutoMP: A Tool to Automate Performance Testing for Model Pla...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Zhe Yang Wei He Fenglong Cai Yonghui Xu Wei Guo Lizhen Cui School of Software Shandong University Jinan China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

As AI applications are widely deployed in various fields, the computing cost of AI is skyrocketing. The high cost not only puts pressure on the environment but also poses challenges for researchers entering the field of deep learning. Green AI is gradually gaining attention, aiming to reduce computing costs and make AI application deployment more efficient and environmentally friendly. However, due to the wide variety of deep learning models, there are many challenges in efficiently deploying multiple models on GPUs. An unreasonable model deployment strategy will lead to insufficient utilization of GPU computing resources. We address some of these challenges through AutoMP, a tool that automates performance testing for model placement on GPUs. Through AutoMP, researchers can flexibly initiate a large number of experiments to study which models are suitable for inference tasks on the same GPU, thereby making GPU utilization more efficient. AutoMP provides a user-friendly visual interface and an API to meet users’ needs in different scenarios. AutoMP also provides a complete experimental analysis tool that generates visual charts of experimental data from multiple dimensions and gives experimental conclusions to assist researchers in making decisions. To date, AutoMP has been used by a large number of users for empirical research on deep learning model placement. The cumulative number of experiments has exceeded 10,000. The flexibility and extensibility of AutoMP and our own experience using it show that this tool plays a vital role in promoting Green AI.

关键词： Deep learning Visualization distributed processing Costs Computational modeling Green products Graphics processing units Extensibility Artificial intelligence Testing

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Adaptive Prefetching for Fine-grain Communication in PGAS Programs

Adaptive Prefetching for Fine-grain Communication in PGAS Pr...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Thomas B. Rolinger Alan Sussman NVIDIA Austin TX USA University of Maryland College Park MD USA

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Applications that require distributed-memory systems and exhibit irregular memory access patterns present both productivity and performance challenges. This is largely due to the fine-grain communication that arises from irregular memory accesses to distributed data. The Partitioned Global Address Space (PGAS) model provides a globally shared address space and one-sided communication, making it well suited for implementing irregular codes. However, while the PGAS model provides productivity advantages, irregular applications have difficulty achieving high performance due to the cost of fine-grain remote accesses. One way to improve the performance of such PGAS programs is to prefetch remote data before it is needed, thereby hiding communication latency. The challenges of applying prefetching are computing the prefetch distance (i.e., how far ahead to issue prefetches), determining when prefetching will be profitable, and modifying the program to perform prefetching. In this work, we present an adaptive prefetching optimization that can be applied to PGAS programs with irregular memory access patterns. We target the Chapel parallel programming language, which implements a PGAS model. Our optimization leverages runtime information to adjust the prefetch distance and to pause/resume prefetching when that is likely to provide performance gains. Furthermore, we develop compiler support to automatically apply the optimization without requiring user intervention. We evaluate the optimization across five different distributed-memory systems and four workloads. We observe runtime speed-ups of 0.5 – 377x for the Chapel workloads when compared to not prefetching, and 3 – 215x when compared to implementations written in UPC, OpenSHMEM, and one-sided MPI.

关键词： Productivity distributed processing Runtime parallel programming Prefetching Memory management distributed databases

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Accelerating Quantum Light-Matter Dynamics on Graphics Processing Units

Accelerating Quantum Light-Matter Dynamics on Graphics Proce...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Taufeq Mohammed Razakh Thomas Linker Ye Luo Rajiv K. Kalia Ken-Ichi Nomura Priya Vashishta Aiichiro Nakano Collaboratory for Advanced Computing and Simulations University of Southern California Los Angeles CA USA Stanford PULSE Insitute SLAC National Accelerator Laboratory Menlo Park CA USA Computational Science Division Argonne National Laboratory Lemont IL USA

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

To study light-matter interaction, we have developed a linear-scaling DC-MESH (divide-and-conquer Maxwell-Ehrenfest-surface hopping) simulation algorithm, where our globally-sparse and locally-dense electronic solvers, multiple time-scale splitting, and shadow dynamics achieve high scalability and allow the most compute-intensive quantum dynamics kernel based on time-dependent density functional theory to reside on GPU with minimal CPU-GPU data transfer. GPU computation based on OpenMP target constructs is accelerated by: (i) data and loop reordering for better memory access patterns; (ii) hierarchical GPU offloading using teams-distribute and parallel constructs, respectively, for coarse and fine computations; (iii) algebraic ‘BLASification’ of the nonlocal computational bottleneck; and (iv) GPU-resident data structures facilitated by custom C++ class initializer and destructor based on OpenMP target data constructs. We have thereby achieved 644-fold speedup on Nvidia A100 GPU over AMD EPYC 7543 CPU of the Polaris computer at Argonne Leadership computing Facility. In addition, the DC-MESH code exhibits a weak-scaling parallel efficiency of 96.73% on 256 nodes (or 1,024 GPUs) of Polaris for 5,120-atom PbTiO 3 material. This enables the study of light-induced topological switching for future ultrafast and ultralow-power ferroelectric topotronics applications.

关键词： Leadership Codes Quantum computing Heuristic algorithms Scalability Graphics processing units Switches

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DMSA: Decentralized and Multi-keyword Selective Data Sharing and Acquisition

DMSA: Decentralized and Multi-keyword Selective Data Sharing...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Moheng Lin Peichang Shi Xiang Fu Feng Jiang Guodong Yi National Key Laboratory of Parallel and Distributed Computing College of Computer Science National University of Defense Technology Changsha China Xiangjiang Lab Changsha China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Blockchain technology has been extensively uti-lized in decentralized data-sharing applications, with the immutability of blockchain providing a witness for the circulation of data. However, current blockchain data-sharing solutions still fail to address the simultaneous screening needs of both the sender and receiver with multi-keywords. Without the capability to support bilateral simultaneous filtering, the disclosure of reasons for matching failures could inadvertently expose sensitive user data. Therefore, the challenge lies in enabling ciphertexts with multiple keywords and receivers with multiple interests to achieve mutual and simultaneous matching. Based on the technical foundations of SE (Searchable Encryption), MABE (Multi-Attribute Based Encryption), and polynomial fitting, this paper proposes a scheme called DMSA (Decentralized and Multi-keyword selective Sharing and selective Acquisition). This scheme can satisfy soundness, enabling ciphertexts carrying multiple keywords and receivers representing multiple interests to match each other simultaneously. We conducted a security analysis that confirms the security of DMSA against chosen-plaintext attacks. Our experimental results demonstrate a significant efficiency improvement, with a 67% increase over single-keyword data-sharing schemes and a 16% enhancement compared to the existing multi-keyword data-sharing solution.

关键词： distributed processing Filtering Data security Keyword search Fitting Receivers Polynomials Data models Blockchains Encryption

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A distributed, Asynchronous Algorithm for Large-Scale Internet Network Topology Analysis

A Distributed, Asynchronous Algorithm for Large-Scale Intern...

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IEEE/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Youssef Elmougy Akihiro Hayashi Vivek Sarkar Georgia Institute of Technology Atlanta GA USA

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

With the growing complexity of modern internet networks, we introduce a distributed, asynchronous, and scalable algorithm tailored for determining the centrality and importance of various levels of the global internet network topology at a massive scale. By utilizing triangle formations and neighborhood densities in these complex networks, our algorithm provides valuable insights into the structural importance of individual nodes and the intricate relationships among interconnected entities. Focusing on the global internet's prime components — routers, IP addresses, and Autonomous Systems — the algorithm provides a scalable solution extending to the global internet infrastructure, datacenters, cloud networks, and private networks. By taking advantage of the parallelism, distributed processing, efficient communication, and fine-grained asynchronous execution through an Actor-based programming system, our algorithm is capable of efficiently processing and performing rapid computations on large-scale internet networks. We perform scalability studies on the NERSC Perlmutter supercomputer and the Georgia Tech HPC PACE cluster using three large-scale real-world network datasets and one large-scale synthetic network dataset, achieving up to 91.7% parallel efficiency scaling out to 2K cores and reducing execution time from 5.7 hours to 18.3 seconds, while performing 105.4× better on average compared to related approaches. Our research contributes significantly to facilitating enhanced network management, fault tolerance and resilience, and security, but as well to improving overall network stability, reducing latency, and optimizing energy consumption across the vast internet network devices environment.

关键词： Performance evaluation Cloud computing Scalability Clustering algorithms Programming parallel processing Supercomputers Stability analysis Security Resilience

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A Runtime Manager Integrated Emulation Environment for Heterogeneous SoC Design with RISC-V Cores

A Runtime Manager Integrated Emulation Environment for Heter...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Suluhan, H. Umut Gener, Serhan Fusco, Alexander Mack, Joshua Dagli, Ismet Belviranli, Mehmet Edemen, Cagatay Akoglu, Ali Univ Arizona Elect & Comp Engn Dept Tucson AZ 85721 USA Colorado Sch Mines Comp Sci Dept Golden CO 80401 USA Ozyegin Univ Elect & Elect Engn Dept Istanbul Turkiye

ISBN: (纸本)9798350364613;9798350364606

RISC-NI based architectures have gained attention for deployment on platforms from SoC to HPC scale to meet the demands of a wide range of computational workloads that may require specialized hardware tailored to their specific performance goals. In previous works, we introduced CEDR, an opensource, unified compilation and runtime framework designed to facilitate productive hardware-agnostic application deployment on heterogeneous architectures, and lift the barriers to research on the design and evaluation of scheduling heuristics and accelerators for heterogeneous systems. In this study, we demonstrate the capability of CEDR in supporting heterogeneous systems composed of RISC-V cores and a pool of accelerators. We investigate the impact of employing customized lightweight RISC-V cores for managing accelerators individually. Such management approach, compared to centralized accelerator management model, scales down the stress on the runtime environment where compute resources are shared among multiple applications each with varying degrees of task-level parallelism. We perform evaluations on a heterogeneous SoC emulated on the Xilinx Virtex-7 FPGA based on execution of applications from radar, signal processing, and autonomous vehicles domains. We observe that releasing CPU-based compute cores from accelerator management through lightweight RISC-V cores results with up to 47% reduction in time spent on accelerator management. Since CPU-based compute cores exclusively become available for application task execution and contention on resource management is reduced, we observe speedup of up to 2.2x in application execution time based on experiments conducted with workloads consisting of dynamically arriving real-life application scenarios.

关键词： Terms Heterogeneous computing resource management runtime systems accelerators RISC -V

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EduPar Virtual Poster Session

EduPar Virtual Poster Session

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Camara, Jesus Cano, Jose-Carlos Cuenca, Javier Maeda, Toshiyuki Saura-Sanchez, Mariano Tseng, Lewis Wakatani, Akiyoshi Barnas, Martina Univ Murcia Dept Engn & Technol Comp Murcia Spain Hannan Univ Fac Management Informat Matsubara Osaka Japan Tech Univ Cartagena Dept Mech Engn Cartagena Spain Boston Coll Comp Sci Boston MA USA Konan Univ Fac Intelligence & Informat Kobe Hyogo Japan Indiana Univ Comp Sci Bloomington IN USA

ISBN: (纸本)9781665435772

This paper provides an overview of posters accepted for the EduPar 21 poster session. Poster sessions have been an important part of the EduPar workshops, providing an opportunity to facilitate interactions and fostering the community. After a hiatus caused by the COVID-19 pandemic we decided to resume the poster session tradition and to hold the first virtual poster session in EduPar's eleven years history.

关键词： parallel computing Education Engineering Education Data Science Education Curriculum Design Assignments Pedagogical issues Pedagogical tools

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Time-Division Multiplexing for FPGA Considering CNN Model Switch Time

Time-Division Multiplexing for FPGA Considering CNN Model Sw...

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Nakamura, Tetsuro Saito, Shogo Fujimoto, Kei Kaneko, Masashi Shiraga, Akinori NTT Network Serv Syst Labs Tokyo Japan

ISBN: (纸本)9781665435772

With the spread of real-time data analysis by artificial intelligence (AI), the use of accelerators in edge computing has been attracting attention due to their low power consumption and low latency. In this paper, we propose a system that further reduces the power consumption and cost by sharing an accelerator among multiple users while maintaining real-time performance. Four requirements are defined: high utilization of device, fair device usage among users, real-time performance, and resource abstraction. Targeting a use case of AI inference, we propose a system that can share a field-programmable gate array (FPGA) among multiple users while satisfying the requirements by switching convolutional neural network (CNN) models stored in the device memory on the FPGA. The system enables a time-division multiplexed accelerator with real-time performance and high device utilization by using a scheduling algorithm that considers the switch time of the CNN models. User fairness is also achieved by adopting ageing techniques in the scheduling algorithm, in which priority increases in accordance with job waiting time. In addition, a thread manager has been integrated to the system that absorbs the difference among CNN models to abstract underlying hardware resources. The system was implemented on an FPGA device and evaluated to be 24-94 % fairer and 31-33 % more resource efficient than the conventional system using first-come first-served and round robin algorithms.

关键词： FPGA Edge computing Scheduler Convolutional Neural Network Time Multiplexing

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