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AQMFL: An Adaptive Quantization Framework for Multi-modal Federated Learning in Heterogeneous Edge Devices

AQMFL: An Adaptive Quantization Framework for Multi-modal Fe...

引用

international symposium on parallel and distributed Processing with Applications, ISPA

作者： Haoyong Tang Kaixuan Zhang Jiuwu Zhang Xin Xie Xinyu Tong Xiulong Liu College of Intelligence and Computing Tianjin University China Tianjin Key Laboratory of Advanced Networking (TANK)

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

With the wide application of multi-modal fusion sensing in scenarios such as autonomous driving and human-computer interaction, the privacy security and communication burden caused by massive data uploading need to be solved urgently. Federated Learning (FL) has received significant attention as a privacy-preserving distributed machine learning paradigm. Recent Multi-Modal Federated Learning (MMFL) focuses on addressing modal heterogeneity to enhance accuracy and speed up convergence. However, it overlooks the huge communication overhead in updating complex multi-modal network models, especially in edge environments with limited bandwidth. At the same time, the state-of-the-art communication-efficient FL methods are not customized to the MMFL characteristics. In this paper, we propose the Adaptive Quantization framework for Multi-modal Federated Learning (AQMFL). AQMFL implements decision-level multi-modal fusion locally by using parallel training and model ensemble, supporting its adaptation to modal heterogeneity and flexible deployment. AQMFL can adaptively allocate the number of quantization levels of gradient according to the modal contribution and the heterogeneous communication ability of nodes, which speeds up the system convergence and achieves a better balance between accuracy and communication efficiency. Compared with the classical baselines, AQMFL can reduce the total communication overhead by up to 50.47% and the total training time by up to 52.11% while maintaining the accuracy.

关键词： Training Human computer interaction Adaptation models distributed processing Quantization (signal) Accuracy Federated learning Sensors Security Convergence

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MultiGrid on FPGA Using Data parallel C++ 36

MultiGrid on FPGA Using Data Parallel C++

引用

36th IEEE international parallel and distributed Processing symposium Workshops, IPDPSW 2022

作者： Siefert, Christopher Olivier, Stephen L. Voskuilen, Gwendolyn Young, Jeffrey Sandia National Laboratories AlbuquerqueNM United States Georgia Institute of Technology AtlantaGA United States

ISBN: (纸本)9781665497473

Centered on modern C++ and the SYCL standard for heterogeneous programming, Data parallel C++ (dpc++) and Intel's oneAPI software ecosystem aim to lower the barrier to entry for the use of accelerators like FPGAs in diverse applications. In this work, we consider the usage of FPGAs for scientific computing, in particular with a multigrid solver, MueLu. We report on early experiences implementing kernels of the solver in DPC++ for execution on Stratix 10 FPGAs, and we evaluate several algorithmic design and implementation choices. These choices not only impact performance, but also shed light on the capabilities and limitations of DPC++ and oneAPI. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Orchestrating Bag-of-Tasks Applications with Dynamically Spawned Tasks in a distributed Environment

Orchestrating Bag-of-Tasks Applications with Dynamically Spa...

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international symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS)

作者： Stavrinides, Georgios L. Karatza, Helen D. Aristotle Univ Thessaloniki Dept Informat Thessaloniki Greece

ISBN: (纸本)9781713831419

As the distributed computing paradigm continues to evolve due to advances such as cloud and fog computing, the need for effective workload allocation on distributed resources has become more imperative than ever. However, workload orchestration in distributed environments poses many challenges, especially in the case where the workload comprises jobs consisting of parallel component tasks. A particularly challenging scenario in the context of such bag-of-tasks applications, is the case where a component task produces an output that does not meet a predefined Quality of Service (QoS) threshold. In such a case, a new task is dynamically spawned at runtime, in order to carry out the additional computational work required for producing an acceptable result. In order to leverage data locality, the dynamically spawned task must be assigned to the same resource as the previous task that failed to meet the QoS requirements. Consequently, it is important to examine how a such dynamically changing workload affects the performance and load balancing of the distributed resources. To this end, in this paper we investigate the orchestration of bag-of-tasks applications with dynamically spawned tasks in a distributed environment. Three task routing techniques are studied and compared using simulation, under various load cases.

关键词： workload orchestration resource assignment load balancing bags-of-tasks dynamically spawned tasks distributed environment

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Coded parallelism for distributed Deep Learning

Coded Parallelism for Distributed Deep Learning

引用

IEEE international symposium on Information Theory

作者： Songting Ji Zhaoyang Zhang Zhaohui Yang Richeng Jin Qianqian Yang College of Information Science and Electronic Engineering Zhejiang University Hangzhou China Zhejiang Provincial Key Laboratory of Info. Proc. Commun. & Netw. (IPCAN) Hangzhou China International Joint Innovation Center Zhejiang University Haining China

With the rapid development of deep learning, the parameters of modern neural network models, especially in the field of Natural Language Processing (NLP) are extremely huge. When the parameters of the model are larger even than the storage memory of a single device, it is necessary to split the original big learning model into different parts with each part assigned to one device, thus realizing joint model training over different devices (i.e., distributed training). In this paper, we aim to introduce the advanced coding scheme into the distributed parallel framework, which leads to the perfect combination of coding and the underlying calculation of neural networks. The proposed scheme is not only able to avoid the impact of poor computing power or low bandwidth and even dropped devices (stragglers) on system performance but also reduce the communication load between different devices, thereby greatly improving the performance of distributed parallel systems.

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SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs

SWEEP: Adaptive Task Scheduling for Exploring Energy Perform...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Jing Chen Madhavan Manivannan Bhavishya Goel Miquel Pericàs Department of Computer Science and Engineering Chalmers University of Technology

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Energy efficiency is becoming a major concern when running parallel computing systems owing to its impact on system reliability and operating cost. Recent works, that focus on energy efficient execution of task-based parallel applications on multi-core systems, leverage a subset of architectural features (core asymmetry, CPU DVFS and memory DVFS) and application attributes (inter-task parallelism, intra-task parallelism and task characteristics) to achieve this goal. More importantly, they have a fixed target metric and do not provide the flexibility to explore energy performance trade-offs (EPTO). We propose SWEEP, a task scheduler that leverages all the aforementioned architectural knobs and application attributes to facilitate EPTO exploration. SWEEP, at a high level, uses a combination of models and heuristics and works by splitting application execution into high parallelism and low parallelism phases. It then uses an adaptive task distribution algorithm, specific to the phase type, that leverages model-based predictions to determine the best task schedule and the DVFS settings for the phase. Moreover, SWEEP is able to flexibly target various EPTO metrics, a feature that is not supported by other proposals. Our evaluation shows that SWEEP achieves 19.9%, 36.4% and 9.5% reduction on average in terms of EDP, ED 2 P and E 2 DP compared to the best performing state-of-the-art.

关键词： Measurement Adaptation models Schedules Multicore processing parallel processing Predictive models Prediction algorithms

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A Scalable Mapping Method for Elastic CGRAs

A Scalable Mapping Method for Elastic CGRAs

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Makoto Saito Takuya Kojima Hideki Takase Hiroshi Nakamura Graduate School of Information Science and Technology The University of Tokyo Tokyo Japan

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

There is a growing expectation for accelerating high performance computing (HPC) applications using Coarse-Grained Reconfigurable Arrays (CGRAs). A large processing element (PE) array is necessary in such a scenario. When executing an application on CGRAs, instructions in the application kernel are mapped onto the PEs. The mapping time increases exponentially with the number of PEs and the instructions. Elastic CGRA is a type of CGRA where PEs can exchange data with each other asynchronously using a handshake protocol. Thanks to the scheduling of instructions performed by the hardware, Elastic CGRA possibly improves PE utilization compared to traditional CGRAs. In addition, it alleviates the complexity of the mapping problem since there is no need for explicit timeslot allocation when mapping time. However, given a large PE array suitable for HPC platforms, Elastic CGRA still suffers from a long mapping time. In order to accommodate as many application kernels into the PE array as possible within practical time, we propose a scalable mapping method exploiting data-level parallelism and thread-level parallelism. The proposed method divides the mapping process into two phases. In the first phase, the target application kernel is mapped in a conventional manner while changing the available PE array size, and then each mapping result is stored in a mapping database. The next phase replicates the mapping in the database and relocates them to fill the whole PE array. Instead of mapping pre-unrolled kernels, the proposed method efficiently prunes search space at the slight expense of optimality. The evaluation results demonstrate that the conventional approach can treat up to a 7x7 PE array within a practical time, whereas the proposed method extends the available array size to 80x80.

关键词： Phased arrays distributed processing Protocols Databases Scalability High performance computing parallel processing

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Scaling Sparse Matrix Multiplication on CPU-GPU Nodes 35

Scaling Sparse Matrix Multiplication on CPU-GPU Nodes

引用

35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Xia, Yang Jiang, Peng Agrawal, Gagan Ramnath, Rajiv Ohio State Univ Comp Sci & Engn Columbus OH 43210 USA Univ Iowa Comp Sci Dept Iowa City IA USA Augusta Univ Comp & Cyber Sci Augusta GA USA

ISBN: (纸本)9781665440660

Multiplication of two sparse matrices (SpGEMM) is a popular kernel behind many numerical solvers, and also features in implementing many common graph algorithms. Though many recent research efforts have focused on implementing SpGEMM efficiently on a single GPU, none of the existing work has considered the case where the memory requirements exceed the size of GPU memory. Similarly, the use of the aggregate computing power of CPU and GPU has also not been addressed for those large matrices. In this paper, we present a framework for scaling SpGEMM computations for matrices that do not fit into GPU memory. We address how the computation and data can be partitioned amass kernel executions on GPUs. An important emphasis in our work is overlapping data movement and computation. We achieve this by addressing many challenges, such as avoiding dynamic memory allocations, and re-scheduling data transfers with the computation of chunks. We extend our framework to make efficient use of both GPU and CPU, by developing an efficient work distribution strategy. Our evaluation on 9 large matrices shows that our out-of-core GPU implementation achieves 1.98-3.03X speedups over a state-of-the-art multi-core CPU implementation, our hybrid implementation further achieves speedups up to 3.74x, and that our design choices are directly contributing towards achieving this performance.

关键词： distributed processing Distribution strategy Memory management Graphics processing units Data transfer Dynamic scheduling Sparse matrices

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A Fast Scalable Hardware Priority Queue and Optimizations for Multi-Pushes

A Fast Scalable Hardware Priority Queue and Optimizations fo...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Samuel Collinson Allan Bai Oliver Sinnen Department of Electrical Computer and Software Engineering Parallel and Reconfigurable Computing Lab University of Auckland New Zealand

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Priority queues (PQ) are an essential data structure for many important algorithms. Hardware implementations of priority queues can accelerate such algorithms significantly. Usually a choice has to be made between very fast (fixed-size) hardware PQs or scalable PQs. Fast hardware queues can provide single cycle push and pop operations, but are limited in size. Scalable hardware queues use embedded memory to achieve scalability, but thereby compromise on speed. This paper proposes a fast and scalable hardware priority queue that can be used for general purpose. It is based on a modular and flexible hybrid design, using a shift register queue combined with a heap-based queue. In the best case, i.e. when only the first queue is needed, push and pop operations only take a single cycle. In an experimental evaluation on a Xilinx FPGA we demonstrate that performance of the hybrid queue maintains a good balance between performance and scalability even for applications where the size of the working set of data can have large variance. We further propose an optimisation of the heap-based queue to support workloads that repeat several consecutive push operations followed by a single pop operation, which is the workload, for instance, in state space search or ray-tracing.

关键词： distributed processing Scalability Sociology Ray tracing Shift registers Data structures Hardware

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Using Hyperdimensional computing to Extract Features for the Detection of Type 2 Diabetes

Using Hyperdimensional Computing to Extract Features for the...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Neftali Watkinson Divya Devineni Victor Joe Tony Givargis Alexandru Nicolau Alexander Veidenbaum Department of Computer Science and Engineering University of California Riverside Riverside USA UCI Medical Center University of California Irvine Irvine USA Department of Computer Science University of California Irvine Irvine USA

Diabetes impacts around 8% of the world’s population, with Type 2 diabetes comprising up to 90% of cases. This chronic disease is characterized by a metabolic resistance to insulin which results in a high blood sugar level and increased potential for serious health complications. Preventative medicine and the detection of genetic predisposition play a key part in successful treatment. Although several factors have been identified as possible indicators of underlying diabetes, they are not the same in every patient. There have been different approaches to producing predictive models that could help identify risk of onset diabetes. Models built using Machine Learning algorithms have showed promise in the past in detecting relevant features in sample datasets with data from patients at risk of developing diabetes. However, overall performance has not been consistent across datasets. In this paper we describe a feature extraction approach using Hyperdimensional computing as a tool for improving already existing classification models. We tested our approach using two public datasets and compare across several state of the art models. Our approach improves poor performing models while fine tuning models with a high classification accuracy.

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Matrix Engines for High Performance computing: A Paragon of Performance or Grasping at Straws? 35

Matrix Engines for High Performance Computing: A Paragon of ...

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Domke, Jens Vatai, Emil Drozd, Aleksandr Chen, Peng Oyama, Yosuke Zhang, Lingqi Salaria, Shweta Mukunoki, Daichi Podobas, Artur Wahib, Mohamed Matsuoka, Satoshi RIKEN CCS Kobe Hyogo Japan Natl Inst Adv Ind Sci & Technol Tokyo Japan KTH Royal Inst Technol Stockholm Sweden Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781665440660

Matrix engines or units, in different forms and affinities, are becoming a reality in modern processors;CPUs and otherwise. The current and dominant algorithmic approach to Deep Learning merits the commercial investments in these units, and deduced from the No.1 benchmark in supercomputing, namely High Performance Linpack, one would expect an awakened enthusiasm by the HPC community, too. Hence, our goal is to identify the practical added benefits for HPC and machine learning applications by having access to matrix engines. For this purpose, we perform an in-depth survey of software stacks, proxy applications and benchmarks, and historical batch job records. We provide a cost-benefit analysis of matrix engines, both asymptotically and in conjunction with state-of-the-art processors. While our empirical data will temper the enthusiasm, we also outline opportunities to misuse these dense matrix-multiplication engines if they come for free.

关键词： Deep learning Program processors Tensors Machine learning algorithms Benchmark testing Throughput Supercomputers

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