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Profiling HPC Applications with Low Overhead and High Accuracy 19

Profiling HPC Applications with Low Overhead and High Accura...

引用

19th IEEE international symposium on parallel and distributed Processing with Applications (IEEE ISPA)

作者： Zhao, Jingyuan Liu, Xin Liu, Yao Jiao, Penglong Liu, Jinshuo Xue, Wei East China Normal Univ Sch Data Sci & Engn Shanghai Peoples R China Natl Res Ctr Parallel Comp Engn & Technol Beijing Peoples R China Wuhan Univ Sch Cyber Sci & Engn Wuhan Peoples R China East China Normal Univ Shanghai Key Lab Multidimens Informat Proc Shanghai Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781665435741

As the parallel scale of HPC applications represented by earth system models becomes larger and the computing cost becomes higher, the performance of HPC applications is increasingly critical. Profiling HPC applications accurately helps to model the applications and find the performance bottlenecks. However, due to the complexity of HPC applications, the diversity of programming languages, the differences of individual programming habits, and multiple architectures, accurate profiling becomes very tough. In this paper, we propose LPerf: a low-overhead and high-accuracy profiler for HPC applications. To reduce the profiling overhead and improve the profiling accuracy, we propose a preprocessing method which can automatically instrument with tunable granularity thus significantly reducing the run-time overhead of profiling, an aggregated caller-callee relationship which is used to locate relationship of functions efficiently, and a profiling-aware method which can precisely calculate running time of functions. The experimental results show that the error rate of profiling reaches 0.02%, and the overhead reaches 1.6%, in the earth system model named CAS-ESM. Compared with the baselines, the precision, accuracy, and overhead of LPerf have reached the state of the art.

关键词： LLVM instrumentation profiling performance modeling

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Application-Attuned Memory Management for Containerized HPC Workflows

Application-Attuned Memory Management for Containerized HPC ...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Moiz Arif Avinash Maurya M. Mustafa Rafique Dimitrios S. Nikolopoulos Ali R. Butt Rochester Institute of Technology Virginia Tech

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

High-Performance computing (HPC) jobs consist of data and memory-intensive tasks often executed as workflows or ensembles to facilitate efficient and coordinated execution. These workflows are traditionally executed on HPC systems and have unique memory requirements based on the data size, computational complexity, and I/O activity. Recently containerized execution of these workflows has been extensively explored. Containerized workflow execution of HPC jobs requires several terabytes of memory that exceed node capacity, resulting in excessive data swapping to slower storage, degraded job performance, and failures. Similarly, colocated bandwidth-intensive, latency-sensitive, or short-lived workflows suffer from degraded performance due to contention, memory exhaustion, and higher access latency due to suboptimal memory allocation. Recently, tiered memory systems comprising persistent memory and compute express link (CXL) have been explored to provide additional memory capacity and bandwidth to memory-constrained systems and applications. However, current memory allocation and management techniques for tiered memory subsystems are inadequate to meet the diverse needs of colocated containerized jobs in HPC systems that concurrently run workflows and ensembles at scale. This paper leverages tiered memory systems for containerized HPC workflows and proposes efficient memory management policies including intelligent page placement and eviction policies to improve memory access performance. Our page allocation and replacement policies incorporate task characteristics and enable efficient memory sharing between workflows. We integrate our policies with the popular HPC scheduler, SLURM, and container runtime, Singularity, to show that our approach improves tiered memory utilization and application performance and reduces workflow execution times by up to 51%, 87%, and 35% as compared to the ideal, realistic, and optimized tiered execution environments, respectively.

关键词： Concurrent computing distributed processing Runtime Scalability High performance computing Memory management Bandwidth

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UnifyFS: A User-level Shared File System for Unified Access to distributed Local Storage

UnifyFS: A User-level Shared File System for Unified Access ...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Michael J. Brim Adam T. Moody Seung-Hwan Lim Ross Miller Swen Boehm Cameron Stanavige Kathryn M. Mohror Sarp Oral Oak Ridge National Laboratory USA Lawrence Livermore National Laboratory USA

We introduce UnifyFS, a user-level file system that aggregates node-local storage tiers available on high performance computing (HPC) systems and makes them available to HPC applications under a unified namespace. UnifyFS employs transparent I/O interception, so it does not require changes to application code and is compatible with commonly used HPC I/O libraries. The design of UnifyFS supports the predominant HPC I/O workloads and is optimized for bulk-synchronous I/O patterns. Furthermore, UnifyFS provides customizable file system semantics to flexibly adapt its behavior for diverse I/O workloads and storage devices. In this paper, we discuss the unique design goals and architecture of UnifyFS and evaluate its performance on a leadership-class HPC system. In our experimental results, we demonstrate that UnifyFS exhibits excellent scaling performance for write operations and can improve the performance of application checkpoint operations by as much as 3× versus a tuned configuration.

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Leveraging SmartNIC for Ring AllReduce Offloading

Leveraging SmartNIC for Ring AllReduce Offloading

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Lihuan Hui Wang Yang Yanbo Wang School of Computer Science and Engineering Central South University

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Efficient collective communication, particularly all-reduce operations, is of paramount importance for parallel computing applications like large-scale distributed learning and communication-intensive scientific applications. However, existing optimization efforts for collective communication primarily concentrate on offloading the all-reduce onto network switches, known as In-Network Aggregation(INA), demanding substantial system customization. Unfortunately, these INA solutions are generally incompatible with existing HPC applications that utilize MPI for message passing, except for SHARP and *** by our systematic analysis, we identified two key factors that impact the performance of the naïve ring all-reduce operation: i. The all-reduce computation process frequently interrupts the GPU/CPU’s computation tasks; ii. The GPU/CPU is, in fact, indifferent to intermediate computational results. Based on these insights, this paper proposes DirectReduce, a fully offloading ring all-reduce architecture that is comprised of three components: (i) the GateKeeper module, responsible for evaluating outgoing data to decide its progression-either directing it to the Protocol Engine for packetization or intercepting it for reduction (e.g., sum, maximum); (ii) the DataDirector module, which classifies the incoming data either is for intermediate result reduction or final result storage; and (iii) the ComputeEnhancer module, designed to execute reduction operations directly on the SmartNIC. Extensive simulation results show that DirectReduce can reduce latency by up to 1.98X in a ring topology and 1.75X in a 6D-torus topology compared to the naïve ring all-reduce.

关键词： Systematics Protocols Distance learning Simulation Message passing Logic gates parallel processing Topology Optimization Engines

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Vapor: A GPU Sharing Scheduler with Communication and Computation Pipeline for distributed Deep Learning 19

Vapor: A GPU Sharing Scheduler with Communication and Comput...

引用

19th IEEE international symposium on parallel and distributed Processing with Applications (IEEE ISPA)

作者： Zhu, Xiaorui Gong, Lei Zhu, Zongwei Zhou, Xuehai Univ Sci & Technol China Dept Comp Sci & Technol Hefei Anhui Peoples R China Univ Sci & Technol China Suzhou Inst Adv Res Suzhou Peoples R China

ISBN: (纸本)9781665435741

Nowadays, distributed deep learning (DDL) workloads are typically trained on GPU clusters. Modern GPUs support the concurrent execution of multiple jobs to achieve efficient parallelization of computation and communication. While sharing GPU improves resource utilization and cuts down job completion time, interference among co-located jobs results in significant performance degradation. Recent studies such as interference-aware job placement carefully co-locate jobs with the least interference in a best-effort manner and are not ideal. Another challenge in GPU sharing is straggler due to unbalanced workloads in packing. When stragglers occur, GPU resources are wasted, so the training processes are delayed. We present Vapor, a GPU sharing scheduler for distributed deep learning on multi-GPUs featured by two novel scheduling policies: preemptive GPU sharing and adaptive batch redistribution to maximize GPU utilization and improve training efficiency. Firstly, Vapor uses preemptive scheduling that parallels computation and communication of co-located jobs in a pipelined manner. Secondly, Vapor uses an adaptive batch redistribution method to deal with stragglers in packing to improve resource utilization further. Vapor provides an AIMD model to predict the relationship between the batch size of the training data and the model calculation time in each iteration. We evaluate Vapor with other representative schedulers. Experiment on a Kubernetes cluster of 16 Tesla V100 GPU handling with popular DDL jobs shows that Vapor reduces job completion time by 21.8% compared with popular SOTA schedulers.

关键词： Training Schedules parallel computing Load balancing Graphics processing units

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Scalable adaptive algorithms for next-generation multiphase flow simulations

Scalable adaptive algorithms for next-generation multiphase ...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Kumar Saurabh Masado Ishii Makrand A. Khanwale Hari Sundar Baskar Ganapathysubramanian Department of Mechanical Engineering Iowa State University USA School of Computing University of Utah USA Center for Turbulence Research Stanford University USA

High-fidelity flow simulations are indispensable when analyzing systems exhibiting multiphase flow phenomena. The accuracy of multiphase flow simulations is strongly contingent upon the finest mesh resolution used to represent the fluid-fluid interfaces. However, the increased resolution comes at a higher computational cost. In this work, we propose algorithmic advances that aim to reduce the computational cost without compromising on the physics by selectively detecting key regions of interest (droplets/filaments) that require significantly higher resolution. The framework uses an adaptive octree–based meshing framework that is integrated with PETSc’s linear algebra solvers. We demonstrate scaling of the framework up to 114,688 processes on TACC’s Frontera. Finally, we deploy the framework to simulate one of the most resolved simulations of primary jet atomization. This simulation – equivalent to 35 trillion grid points on a uniform grid – is 64× larger than current state–of–the–art simulations and provides unprecedented insights into an important flow physics problem with a diverse array of engineering applications.

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QGIP: A Framework Bridging Quantum Grayscale Image Processing and Applications

QGIP: A Framework Bridging Quantum Grayscale Image Processin...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Xilong Che Jiale Zhang Shuo Chen Shun Peng Juncheng Hu College of Computer Science and Technology Jilin University Changchun China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Quantum computing offers parallel processing capabilities and resource-saving advantages, particularly useful for managing expansive datasets and complex image processing tasks. Grayscale images, being the simplest single-channel image mode, are frequently employed in artificial intelligence training. Before actual image applications, various image processing operations are typically required. However, the restoration of a grayscale image of dimensions 2 n × 2 n after a series of linear transformations poses a challenge. Existing methods typically involve finding the inverse of the most recent linear transformation or re-encoding the image followed by repeated operations until the final transformation, resulting in excessive computational overhead and disconnection from subsequent quantum grayscale image applications. To address this issue, we propose a universal quantum linear restoration algorithm for grayscale image, denoted as QLR, which effectively bridges the stages of linear transformation and subsequent image applications. QLR reduces the time complexity from O(2 n ) to O(n) compared to classical counterpart. Building upon the QLR algorithm, we further propose two quantum resource-optimized compression methods for optional lossless image storage. Combining with other quantum algorithms and techniques, we design a framework (QGIP) aimed at bridging the processes of quantum grayscale image processing and applications. Experiments simulated on the IBM Quantum platform validate the correctness and efficiency of our proposal.

关键词： Training distributed processing Quantum algorithm Image coding Gray-scale parallel processing Image restoration Proposals Image storage Time complexity

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GrAPL 2022 Keynote Speaker: GraphBLAS Beyond Simple Graphs

GrAPL 2022 Keynote Speaker: GraphBLAS Beyond Simple Graphs

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Tim Mattson Parallel Computing Lab Intel Labs

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GANs-based Signal Quality Assessment for Heart Rate Estimation with Ballistocardiograph

GANs-based Signal Quality Assessment for Heart Rate Estimati...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Ruilin Cai Jun Qi Jiayi Li Jianjun Chen Wei Wang Haiyang Zhang Department of Computing Xi’an JiaoTong-Liverpool University Suzhou China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

The ballistocardiograph (BCG) is a non-contact technology that monitors the heart and provides detailed cardiovascular parameters. Despite its broad applicability for long-term home monitoring due to Covid-19, BCG signals face challenges from positional changes, body movements, and system noise, which impact detection algorithms. In this paper, we propose a method for detecting inter-beat intervals (IBI) based on signal fusion technology. We utilize a Dynamic Bayesian Network (DBN) to integrate five heartbeat localization features extracted from BCG signals. Additionally, Generative Adversarial Networks (GANs) are used to assess signal quality and select correlated channels, improving heart rate monitoring accuracy. Experimental results demonstrate an average coverage of 95.21% and a mean squared error of 0.05. These results outperform those of methods without channel selection and single-channel BCG, indicating the potential for improving IBI estimation in multichannel BCG signal sensor systems.

关键词： Accuracy Noise Estimation Channel estimation Feature extraction Sensor systems Quality assessment Reliability Monitoring Unsupervised learning

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Accelerating Extra Dimensional Page Walks for Confidential computing

Accelerating Extra Dimensional Page Walks for Confidential C...

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IEEE/ACM international symposium on Microarchitecture (MICRO)

作者： Dong Du Bicheng Yang Yubin Xia Haibo Chen Institute of Parallel and Distributed Systems Shanghai Jiao Tong University Engineering Research Center for Domain-Specific Operating Systems (MoE) Shanghai China Institute of Parallel and Distributed Systems Shanghai Jiao Tong University Shanghai AI Laboratory Engineering Research Center for Domain-Specific Operating Systems (MoE) Shanghai China

To support highly scalable and fine-grained computing paradigms such as microservices and serverless computing better, modern hardware-assisted confidential computing systems, such as Intel TDX and ARM CCA, introduce permission table to achieve fine-grained and scalable memory isolation among different domains. However, it also adds an extra dimension to page walks besides page tables, leading to significantly more memory references (e.g., 4 12 for RISC-V Sv39) 1 . We observe that most costs (about 75%) caused by the extra dimension of page walks are used to validate page table pages. Based on this observation, this paper proposes HPMP (Hybrid Physical Memory Protection), a hardware-software co-design (on RISC-V) that protects page table pages using segment registers and normal pages using permission tables to balance scalability and performance. We have implemented HPMP and Penglai-HPMP (a TEE system based on HPMP) on FPGA with two RISC-V cores (both in-order and out-of-order). Evaluation results show that HPMP can reduce costs by 23.1%–73.1% on BOOM and significantly improve performance on real-world applications, including serverless computing (FunctionBench) and Redis.

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