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Design issues of a novel toolkit for parallel application performance monitoring and analysis in cluster and grid environments

Design issues of a novel toolkit for parallel application pe...

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international symposium on parallel Architectures, Algorithms and Networks (ispaN)

作者： Kuan-Ching Li Hsiao-Hsi Wang Chiou-Nan Chen Chun-Chieh Liu Chia-Fu Chang Chia-Wen Hsu Sheng-Shiang Hung Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung Taiwan Laboratory of Bioinformatics and Computational Biology Department of Computer Science National Tsing Hua University Hsinchu Taiwan

The low-cost and availability of network of workstations have made them attractive solution for high performance computing. Striking progress of network technology in enabling high-performance global computing, with the utilization of cluster and grid technologies, in which computational and data resources in a local or wide area network are transparently employed to solve large-scale problems. In this paper, we present implementation and design rationale of Visuel toolkit for performance measurement and analysis of parallel applications, in cluster and grid environments. Most of performance visualization tools available today for high-performance platforms show solely system performance data (e.g., CPU load, memory usage, network bandwidth, server average load), and thus, being suitable for visualisation of computing platform system activities. The Visuel toolkit, is Web-based interface designed to show performance activities of all computing nodes of a cluster or grid computing platform involved in the execution of a parallel application, such as CPU load level and memory usage of each computing node. In addition, this toolkit is able to display comparative performance data visualizations generated from a number of executions of an application under investigation, analyzing the performance of different implementations. Evaluations using this toolkit show that it outperforms in easing the process of investigation and implementation of parallel applications, in effective way.

关键词： Monitoring Performance analysis Grid computing Computer networks Data visualization High performance computing Computer interfaces Concurrent computing Availability Workstations

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HINT: Designing Cache-Efficient MPI_Alltoall using Hybrid Memory Copy Ordering and Non-Temporal Instructions

HINT: Designing Cache-Efficient MPI_Alltoall using Hybrid Me...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： Bharath Ramesh Nick Contini Nawras Alnaasan Kaushik Kandadi Suresh Mustafa Abduljabbar Aamir Shafi Hari Subramoni Dhabaleswar K. D K Panda Department of Computer Science and Engineering The Ohio State University Columbus USA

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Modern multi/many-core processors in HPC systems have hundreds of cores with deep memory hierarchies. HPC applications run at high core counts often experience contention between processes/threads on shared resources such as caches, leading to degraded performance. This is especially true for dense collective patterns, such as MPI_Alltoall, that have many concurrent memory transactions. The ordering of memory copies during the MPI_Alltoall operation can significantly affect performance as cache-efficient access patterns could potentially reduce cache misses. However, the correct access pattern depends on various factors, including cache associativity, cache sizes, coherence protocols, and memory layouts. This paper first identifies sources of bottlenecks in performing memory operations in an Alltoall. We propose different orderings for the memory copies in Alltoall operations and study their effectiveness for various message sizes. We overcome bandwidth bottlenecks related to repeated bus requests in the cache by proposing a hybrid memory copy scheme that combines regular temporal and non-temporal stores. Then, we implement an Alltoall algorithm that dynamically picks between memory orders based on their performance for different message sizes/number of processes. To the best of our knowledge, this is the first work that explores a combination of dynamic memory copy orders and non-temporal instructions for optimizing MPI_Alltoall operations. Our proposed solutions reduce the latency versus state-of-the-art solutions by up to 10x at the micro-benchmark level and 22.2% for the CPU time per loop in distributed Fast Fourier Transforms (FFTs) using P3DFFT.

关键词： distributed processing Protocols Program processors Fast Fourier transforms Heuristic algorithms Layout Coherence

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Accelerating Deep Learning based Identification of Chromatin Accessibility from noisy ATAC-seq Data

Accelerating Deep Learning based Identification of Chromatin...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Narendra Chaudhary Sanchit Misra Dhiraj Kalamkar Alexander Heinecke Evangelos Georganas Barukh Ziv Menachem Adelman Bharat Kaul Parallel Computing Lab Intel Bangalore India parallel Computing Lab Intel Corporation Santa Clara USA Intel Corporation Haifa Israel

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Identifying accessible chromatin regions is a fundamental problem in epigenomics with ATAC-seq being a commonly used assay. Exponential rise in ATAC-seq experiments has made it critical to accelerate processing of ATAC-seq data that can have a low signal-to-noise ratio for various reasons including low coverage or low cell count. To denoise and identify accessible chromatin regions from noisy ATAC-seq data, use of deep learning on 1D data - using large filter sizes, long tensor widths, and/or dilation - has recently been proposed. Convolutions over 1D data consume a majority of the runtime in these methods. However, existing implementations of the 1D convolution layer for CPUs and GPUs fail to efficiently use the underlying architecture especially in the case of large filter sizes, long tensor widths, and dilation. Here, we present ways to accelerate the end-to-end training performance of these deep learning based methods. We evaluate our approach on the recently released AtacWorks toolkit using modern CPUs. Compared to AtacWorks running on an Nvidia DGX-1 box with 8 V100 GPUs, we get up to 2.27× speedup using just 16 CPU sockets. To achieve this, we build an efficient 1D dilated convolution layer and demonstrate reduced precision (BFloat16) training and nearly linear scaling from 1 to 16 sockets. Code Availability: https://***/IntelLabs/Trans-Omics-Acceleration-Library/tree/ATAC-Seq/applications/ATAC-Seq

关键词： Deep learning Convolutional codes Training Tensors Costs Convolution Computer architecture

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Elasticity in a Task-based Dataflow Runtime Through Inter-node GPU Work Stealing

Elasticity in a Task-based Dataflow Runtime Through Inter-no...

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： Joseph John Josh Milthorpe National Computational Infrastructure Canberra Australia School of Computing Australian National University Canberra Australia Oak Ridge National Laboratory Oak Ridge TN USA

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

Most contemporary HPC programming models assume an inelastic runtime in which the resources allocated to an application remain fixed throughout its execution. Conversely, elastic runtimes can expand and shrink resources based on availability and/or dynamic application requirements. In this paper, we implement elasticity for PaRSEC, a task-based dataflow runtime, using inter-node GPU work stealing. In addition to supporting elasticity, we demonstrate that inter-node GPU work stealing can enhance the performance of imbalanced applications by up to 45%.

关键词： Cloud computing Runtime High performance computing Graphics processing units distributed databases Elasticity Programming parallel processing Dynamic scheduling Resource management

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Application of the parallel Accelerating Board Based on ADSP-21062

Application of the Parallel Accelerating Board Based on ADSP...

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2002 international symposium on distributed Computing and applications for Business Engineering and Science

作者： Gao Shu Guo Qingping Gao Jie Computer College ,Wuhan University of Technology ,Wuhan 430063 P.R.C

Firstly, the paper introduces the structure and working principle of the ADSP-21062, the character of the structure and the programming of the parallel accelerating board .Then , taking non-linear transient equation in the temperature field and the Mandelbrot set problem for example, it puts emphasis on the application of the board in the large-scale numeric and non-numeric computation problem. The testing result shows the board is a kind of high-performance parallel processing product , it can be widely used in the fields such as national defense scientific research ,intelligence process and analysis ,simulated training and simulation ,real-time industrial control .

关键词： ADSP-21062 parallel algorithm Domain Decomposition

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MPISE: Symbolic Execution of MPI Programs

MPISE: Symbolic Execution of MPI Programs

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IEEE international Symposim on High Assurance Systems Engineering

作者： Xianjin Fu Zhenbang Chen Yufeng Zhang Chun Huang Wei Dong Ji Wang College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781479981120

Message Passing Interfaces (MPI) plays an important role in parallel computing. Many parallel applications are implemented as MPI programs. The existing methods of bug detection for MPI programs have the shortage of providing both input and non-determinism coverage, leading to missed bugs. In this paper, we employ symbolic execution to ensure the input coverage, and propose an on-the-fly schedule algorithm to reduce the interleaving explorations for non-determinism coverage, while ensuring the soundness and completeness. We have implemented our approach as a tool, called MPISE, which can automatically detect the deadlock and runtime bugs in MPI programs. The results of the experiments on benchmark programs and real world MPI programs indicate that MPISE finds bugs effectively and efficiently. In addition, our tool also provides diagnostic information and replay mechanism to help understand bugs.

关键词： Computer bugs System recovery Switches Synchronization Runtime Testing Scheduling

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Learning from internet: Handling uncertainty in robotic environment modeling 17

Learning from internet: Handling uncertainty in robotic envi...

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9th Asia-Pacific symposium on Internetware, Internetware 2017

作者： Li, Yiying Wang, Huaimin Ding, Bo Che, Huimin National Key Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology ChangSha China

ISBN: (纸本)1595930361

Uncertainty is a great challenge for environment perception of autonomous robots. For instance, while building semantic maps (i.e., maps with semantic labels such as object names), the robot may encounter unexpected objects of which it has no knowledge. It will lead to inevitable failures in traditional environment modeling software. The abundant knowledge being accumulated on the Internet has the potential to assist robots to handle such kind of uncertainty. However, existing researches have not touched this issue yet. This paper proposes a cloud-based semantic mapping engine named SemaCloud, which can not only augment robot's environment modeling capability by the rich cloud resources but also cope with uncertainty by utilizing the Internet knowledge on necessary. It adopts a state-of-art Deep Neural Network (DNN) for real-time and accurate recognition of pre-trained objects. If an object is beyond the knowledge of this DNN, a special mechanism named QoS-aware cloud phase transition is triggered to seek help from existing recognition services on the Internet. By a set of carefullydesigned algorithms, it can maximize benefits and minimize the negative impacts on the Quality of Service (QoS) properties of robotic applications, which is essential to many robot scenarios. The experiments on both open datasets and real robots show that our work can handle uncertainty successfully in robotic semantic mapping without sacrificing critical real-time constraints. © 2017 Association for Computing Machinery.

关键词： Deep neural networks

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Understanding Multi-Dimensional Efficiency of Fine-Tuning Large Language Models Using SpeedUp, MemoryUp, and EnergyUp

Understanding Multi-Dimensional Efficiency of Fine-Tuning La...

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IEEE international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Dayuan Chen Noe Soto Jonas F. Tuttle Ziliang Zong Computer Science Department Texas State University San Marcos USA

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Training large language models (LLMs) from scratch is extremely time-consuming and computationally expensive. Fine-tuning provides an effective approach that skips the initial stages of training and focuses on adapting LLMs to downstream applications with lower demand in resources and reduced cost. A variety of optimizations have been proposed to further optimize the fine-tuning process to reduce training time, memory usage or energy consumption. This introduces a new challenge of selecting the appropriate optimizations that best fit different optimization goals and priorities. This paper presents a detailed analysis of the runtime, memory, and energy efficiency of five optimizations during the three phases of fine-tuning the facebook/opt-350m model, utilizing the DeepSpeed-Chat framework. We propose a framework, comprising of SpeedUp, MemoryUp, and EnergyUp metrics, that can quantitatively evaluate different optimizations across multiple efficiency dimensions. Our research demonstrates that different optimizations have varying impacts on the three efficiency dimensions considered. There is no universally applicable solution to enhance all dimensions simultaneously. Among the five optimizations investigated, ZeRO1 consistently exhibits commendable SpeedUp across all three fine-tuning steps, regardless of hardware resources. Gradient checkpointing excels in MemoryUp during the initial two fine-tuning steps but has the lowest EnergyUp. In addition, current fine-tuning optimizations are not effective in reducing energy consumption. This study provides valuable insights into the selection of appropriate optimizations for runtime, memory usage, and energy consumption during the fine-tuning process of large language models.

关键词： Training Measurement Energy consumption distributed processing Runtime Large language models Memory management

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Hardware for speculative run-time parallelization in distributed shared-memory multiprocessors

Hardware for speculative run-time parallelization in distrib...

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IEEE symposium on High-Performance Computer Architecture

作者： Ye Zhang L. Rauchwerger J. Torrellas Dept. of Comput. Sci. Illinois Univ. Urbana IL USA Computer Science Department Texas A and M University College Station TX USA Computer Science Department University of Illinois Urbana-Champaign IL USA

Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many important applications. Unfortunately, known techniques for run-time parallelization are often computationally expensive or not general enough. To address this problem, we propose new hardware support for efficient run-time parallelization in distributed shared-memory (DSM) multiprocessors. The idea is to execute the code in parallel speculatively and use extensions to the cache coherence protocol hardware to detect any dependence violations. As soon as a dependence is detected, execution stops, the state is restored, and the code is re-executed serially. This scheme, which we apply to loops, allows iterations to execute and complete in potentially any order. This scheme requires hardware extensions to the cache coherence protocol and memory hierarchy of a DSM. It has low overhead. We present the algorithms and a hardware design of the scheme. Overall, the scheme delivers average loop speedups of 7.3 for 16 processors and is 50% faster than a related software-only method.

关键词： Hardware Runtime Circuit simulation Testing Computer science Protocols parallel processing Contracts Processor scheduling Application software

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A Unique Vertex Deleting Algorithm for Graph Isomorphism

A Unique Vertex Deleting Algorithm for Graph Isomorphism

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international symposium on Image and Data Fusion (ISIDF)

作者： Baida Zhang Yuhua Tang Junjie Wu Linqi Huang National laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan P. R. China School of Resources and Safety Engineering Central South University Changsha P. R. China

Graph isomorphism problem has applications in many fields, such as chemistry, computer science, electronics, and network theory. But the exponential complexity of the algorithm makes the testing is time consuming. In this paper, a new algorithm named Unique Vertex Delete (UVD for short) is presented to speed up the process of isomorphic testing. The main idea of UVD algorithm is deleting vertex continuously to reduce the scale of the problem, and new field is added for each vertex to indicate the information of deleted neighbor vertices. Theoretical analysis and experiments show that the UVD algorithm consistently and significantly outperforms existing state-of-the-art approaches.

关键词： Algorithm design and analysis Testing Educational institutions Polynomials Software algorithms Complexity theory Partitioning algorithms

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