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Fast Policy Convergence for Traffic Engineering with Proactive distributed Message-Passing

Fast Policy Convergence for Traffic Engineering with Proacti...

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international symposium on parallel and distributed processing (IPDPS)

作者： Zicheng Wang Zirui Zhuang Jingyu Wang Qi Qi Haifeng Sun Jianxin Liao Beijing University of Posts and Telecommunications Beijing China

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Nowadays, the rise of various network applications makes network traffic become increasingly complex, which brings more stringent requirements to traffic engineering (TE). Although the state-of-the-art TE approaches based on deep reinforcement learning (DRL) or traditional methods can generate optimal solutions for fixed traffic matrices, they cannot converge fast enough to provide real-time optimization in real networks either because of excessive computation times or high communication overheads. Moreover, due to the dynamically changing traffic load on the network, it is also challenging to achieve optimization of maximum link utilization (MLU) and end-to-end delay at the same time since these two optimization objectives may be conflicting, especially when the network is under a low traffic load, which makes the modeling very difficult. To meet these challenges, we present RT-TE, a TE system based on DRL and distributed message-passing between intelligent agents that can achieve real-time optimization for both MLU and end-to-end delay. To reduce the communication time due to link propagation delay during the optimization process, we design a proactive message-passing mechanism that allows agents to use partial messages to compute the routing policy while maintaining the optimization performance. Additionally, to achieve the tradeoff between the two optimization objectives, we model the propagation delay into the DRL model and design a multi-objective training framework with parameter transfer for training. Based on theoretical modeling, we can find the best tradeoff between the two objectives. Moreover, to improve the model's generalization for various traffic flows, we use a GNN model to generate the rewards of the DRL model, which greatly speeds up the training phase and allows us to feed massive amounts of data into the model. Through evaluations of real-world network topologies, our approach shows a 10%-20% improvement in optimizing MLU under short traffic-ch

关键词： Training Computational modeling Telecommunication traffic Quality of service Routing Data models Real-time systems

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LBGK Simulation of Driven Cavity Flow At High Reynolds Numbers

LBGK Simulation of Driven Cavity Flow At High Reynolds Numbe...

引用

2001 international symposium on distributed Computing and applications to Business, Engineering and Science

作者： Baochang Shi,Nengchao Wang,Weibin Guo parallel Computing Institute,Huazhong University of Science and Technology Wuhan 430074,People's Republic of China and Zhaoli Guo National Laboratory of Coal Combustion,Huazhong University of Science and Technology Wuhan 430074,People's Republic of China

Results for viscous,incompressible two-dimensional driven cavity flows were investigated by using a newly developed incompressible LBGK model with a robust boundary-processing scheme with second-order accuracy.A detailed analysis for a range of Reynolds numbers between 5000 and 20000 is *** comparisons with other solutions show that the model gives accurate results over a wide range of Reynolds numbers.

关键词： Driven Cavity Flow Incompressible LBGK Model Nonequilibrium Extrapolation

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Real-time scheduling for 3D GPU rendering

Real-time scheduling for 3D GPU rendering

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international symposium on Industrial Embedded Systems

作者： Stephan Schnitzer Simon Gansel Frank Dürr Kurt Rothermel Institute of Parallel and Distributed Systems University of Stuttgart Germany System Architecture and Platforms Department Daimler AG Germany

3D graphical functions in cars enjoy growing popularity. For instance, analog instruments of the instrument cluster are replaced by digital 3D displays as shown by Mercedes-Benz in the F125 prototype car. The trend to use 3D applications expands into two directions: towards more safety-relevant applications such as the speedometer and towards third-party applications, e.g., from an app store. In order to save cost, energy, and installation space, all these applications should share a single GPU. GPU sharing brings up the problem of providing real-time guarantees for rendering content of time-sensitive applications like the speedometer. To solve this problem, we present a real-time GPU scheduling framework which provides strong guarantees for critical applications while still giving as much GPU resources to less important applications as possible, thus ensuring a high GPU utilization. Since current GPUs are not preemptible, we use the estimated execution time of each GPU rendering job to make the scheduling decisions. Our evaluations show that our scheduler guarantees given real-time constraints, while achieving a high GPU utilization of 97%. Moreover, scheduling is performed highly efficient in real-time with less than 10 μs latency.

关键词： Graphics processing units Three-dimensional displays Rendering (computer graphics) Real-time systems Automotive engineering Automobiles

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A Novel DA-Based parallel Architecture for Inner-Product of Variable Vectors

A Novel DA-Based Parallel Architecture for Inner-Product of ...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Anil Kali Samrat L. Sabat Pramod K. Meher CASEST University of Hyderabad Hyderabad India Department of Computer Science & Engineering C. V. Raman Global University Bhubaneswar India

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Computation of the inner products is frequently used in machine learning (ML) algorithms apart from signal processing and communication applications. distributed arithmetic (DA) has been frequently employed for area-time efficient inner-product implementations. In conventional DA-based architectures, one of the vectors is constant and known a priori. Hence, the traditional DA architectures are not suitable when both vectors are variable. However, computing the inner product of a pair of variable vectors is frequently used for matrix multiplication of various forms and convolutional neural networks. In this paper, we present a novel DA-based architecture for computing the inner product of variable vectors. To derive the proposed architecture, the inner product of any given length is decomposed into a set of short-length inner products, such that the inner product could be computed by successive accumulation of the results of short-length inner products. We have designed a DA-based architecture for the computation of the short-length inner-product of variable vectors and used that in successive clock cycles to compute the whole inner-product by successive accumulation. The post-layout synthesis results using Cadence Innovus with a GPDK 90nm technology library show that the proposed DA-based parallel architecture offers significant advantages in area-delay product and energy consumption over the bit-serial DA architecture.

关键词： Energy consumption Machine learning algorithms Architecture Signal processing algorithms Machine learning Signal processing Vectors

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Static identification of delinquent loads 04

Static identification of delinquent loads

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international symposium on Code Generation and Optimization (CGO)

作者： V.-M. Panait Amit Sasturkar W.-F. Wong Department of Computer Science Politehnica University of Bucharest Romania Department of Computer Science Stony Brook University Stony Brook NY USA Department of Computer Science National University of Singapore Singapore

ISBN: (纸本)9780769521022

The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applications running on RISC-style processors, a small number of delinquent load instructions are responsible for most of the cache misses. Identification of delinquent loads is the key to the success of many cache optimization and prefetching techniques. We propose a method for identifying delinquent loads that can be implemented at compile time. Our experiments over eighteen benchmarks from the SPEC suite shows that our proposed scheme is stable across benchmarks, inputs, and cache structures, identifying an average of 10% of the total number of loads in the benchmarks we tested that account for over 90% of all data cache misses. As far as we know, this is the first time a technique for static delinquent load identification with such a level of precision and coverage has been reported. While comparable techniques can also identify load instructions that cover 90% of all data cache misses, they do so by selecting over 50% of all load instructions in the code, resulting in a high number of false positives. If basic block profiling is used in conjunction with our heuristic, then our results show that it is possible to pin down just 1.3% of the load instructions that account for 82% of all data cache misses.

关键词： Benchmark testing Computer science Prefetching Application software Optimizing compilers parallel processing Hardware Computer aided instruction Runtime Robustness

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Efficient compositing strategies for automotive HMI systems

Efficient compositing strategies for automotive HMI systems

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international symposium on Industrial Embedded Systems

作者： Simon Gansel Stephan Schnitzer Riccardo Cecolin Frank Dürr Kurt Rothermel Christian Maihöfer System Architecture and Platforms Department Mercedes-Benz Cars Division Daimler AG Germany Institute of Parallel and Distributed Systems University of Stuttgart Germany

The relevance of graphical functions in vehicular applications has increased significantly during the last years. Modern cars are equipped with multiple displays used by different applications such as speedometer, navigation system, or media players. The rendered output of the applications is stored in so-called off-screen buffers and then bitblitted to the screen buffer at the respective window sizes and positions. To guarantee the visibility of the potentially overlapping windows, the compositing has to match the z-order of the windows. To this end, two common compositing strategies Tile compositing and Full compositing are used, each having performance issues depending on how windows overlap. Since automotive embedded platforms are restricted in power consumption, installation space, and hardware cost, their performance is limited which effectuates the need for highly efficient bitblitting. In order to increase the performance in compositing the windows, we propose Hybrid Compositing which predicts the required bitblitting time and chooses the most efficient strategy for each pair of overlapping windows. Using various scenarios we show that our approach is faster than the other strategies. In addition, we propose CacheHybrid Compositing which reduces the CPU execution time of our approach by up to 66 %. In case of an automotive scenario we show that our optimized approach saves up to 51% bitblitting time compared to existing approaches.

关键词： Data structures Hardware Libraries Graphics Graphics processing units Predictive models Prediction algorithms

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Concepts for execution time prediction of 3D GPU rendering

Concepts for execution time prediction of 3D GPU rendering

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international symposium on Industrial Embedded Systems

The relevance of graphical functions in vehicular applications has increased significantly during the last years. Modern cars are equipped with multiple displays used by different applications such as speedometer, navigation system, or media players. The recent trend towards hardware consolidation to reduce hardware cost, installation space, and energy consumption, causes graphical 3D applications of different safety-criticality to share a single GPU. This requires effective real-time GPU scheduling concepts to ensure safety and isolation for 3D rendering. Since current GPUs are not preemptible, a deadline-based scheduler must know the GPU execution time of GPU commands in advance. In this work, we present a novel framework to measure and predict the execution time of GPU commands using OpenGL ES 2.0. We present prediction models for the main GPU commands relevant for 3D rendering, namely, FLUSH, CLEAR, and DRAW. For the DRAW command we propose to use the 3D bounding box of the rendered model and apply the vertex shader projection to heuristically estimate the number of fragments rendered. We finally present the implementation and evaluation of our framework, which demonstrates its feasibility and shows that good prediction accuracy can be achieved. In our evaluation using realistic scenarios the absolute prediction error of the DRAW command did not exceed 260 μs.

关键词： Graphics processing units Context Rendering (computer graphics) Predictive models Three-dimensional displays Real-time systems Time measurement

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Emergency Backup for Scientific applications

Emergency Backup for Scientific Applications

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Checkpointing for Supercomputing (SuperCheck), international symposium on

作者： Aniello Esposito Christopher Haine Ali Mohammed EMEA Research Lab Hewlett Packard Enterprise Basel Basel Switzerland

ISBN: (纸本)9781665475730

A framework for the efficient in-network data transfer between a parallel application and an independent storage server is proposed. The case of an unexpected and unrecoverable interruption of the application is considered, where the server takes the role of an emergency backup service preventing the unnecessary loss of valuable information. Workload managers such as SLURM provide a time buffer between the interruption and the termination of an application which can be optimally exploited by the framework making use of RDMA transport and redistribution of data by means of the Maestro middleware. An alternative could consist in a state-of-the-art checkpoint restart mechanism relying on a possibly shared storage hierarchy which suffers from variability and is not scalable in general or in-memory checkpointing which increases memory consumption considerably. Experiments are performed on a HPE/Cray EX system to construct a heuristics for amounts of data that can realistically be backed up during a given time buffer. The method proves to be faster than VELOC and plain MPI-IO using one server node already, for a number of user ranks up to a hundred, with the promise of also better scalability in the long run due to the in-network approach as opposed to filesystem transport.

关键词： Checkpointing Multithreading Scalability Memory management Layout Graphics processing units distributed databases

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Improved SPFA Algorithm Based on Cell-Like P System

Improved SPFA Algorithm Based on Cell-Like P System

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IEEE international symposium on Information (IT) in Medicine and Education, ITME

作者： Hui Zhang Xiyu Liu Laisheng Xiang Business School Shandong Normal University Jinan China

Membrane computing is a fast developing natural computing field with wide applications. Cell-like P system is the one of membrane computing and it is a class of distributed and parallel computing model which is inspired from cell. Then, Shortest Path Faster Algorithm is another name of queue optimization algorithm for the Bellman-Ford algorithm. It is usually used to find single-source shortest paths with negative edges and negative weights. In this paper, we use rewrite rules and dissolution rules of cell-like P system, combined with queue thresholds to improve the SPFA algorithm. We use the average distance between the point where the queue is removed and the point to be queued as the threshold. The node whose distance is less than the threshold is inserted at the beginning of the queue, otherwise, the node is inserted at the end of the queue. A directional weighted digraph is applied to prove the feasibility of the algorithm in this paper. This method takes full advantage of the parallelism of the P system and finds the shortest path with fewer steps and shorter time.

关键词： Optimization Complexity theory Business parallel processing Computational modeling Semiconductor device modeling Approximation algorithms

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On exploiting declarative programming and parallel execution in computer based real-time systems

On exploiting declarative programming and parallel execution...

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international symposium and Workshop on Systems Engineering of Computer Based Systems

作者： B. Lennartsson N. Shahmehri S. Bonnier Carlstedt Elektronik AB Partille Sweden

Presents experiences from modelling real-time applications in the declarative functional language H, developed hand-in-hand with a novel parallel graph reduction architecture called rp8601, both designed with the requirements of real-time embedded systems in mind. In rp8601, the analogue and digital interactions with the environment have been designed into the chips and into the language, and so have mechanisms to handle time constraints. Traditionally, declarative programming means that the programmer need not be aware of the processor operations. Instead, he can focus on the abstract relations between the input and output streams. The specific real-time requirements have normally not been taken into account in the declarative view. Our conclusion is that declarative functional programming is a viable technique for the development of complex software for embedded real-time systems. However, considerable efforts have to be spent on educating and training the application programmers in the new programming paradigm.< >

关键词： parallel programming Concurrent computing Real time systems Programming profession parallel processing Hardware Application software distributed computing Computer industry Time factors

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