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2008 IEEE international symposium on Knowledge Acquisition and Modeling Workshop(KAM 2008)

作者： Chenghui Yang 1 College of Electrical Engineering Northwest University for Nationalities Lanzhou,730030,ChinaChuanjun Ren 2 National Laboratory for parallel & distributed processing College of Computer Science,National University of Defense Technology Changsha,410073,China

Monitoring system always plays the great important role in many kinds of the controlling *** between software and hardware becomes the core problem of the control *** the system,choose the configuration software to develop the monitoring software system,which has features of well graphical *** entire electric locomotive monitoring system include some function module,and the monitoring software locomotive operations recorded by the whole locomotive of the acquisition,the top operations Video Capture,ID card information management,historical data query,print,and other full-featured and easy to *** contorting the main Real-time monitoring system and PLC system to achieve good communication and monitoring *** monitoring software development well on the main station PLC control,greatly improved the electric locomotive of the entire operation by security.

关键词： communication applications control system servicing work safety supervision electric locomotives.

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Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph

Boosting Memory Performance of Many-Core FPGA Device through...

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Annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Yu Bai Abigail Fuentes Michael Riera Mohammed Alawad Mingjie Lin Department of Electrical Engineering and Computer Science University of Central Florida Orlando FL USA

Emerging FPGA device, integrated with abundant RAM blocks and high-performance processor cores, offers an unprecedented opportunity to effectively implement single-chip distributed logic-memory (DLM) architectures [1]. Being “memory-centric”, the DLM architecture can significantly improve the overall performance and energy efficiency of many memory-intensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an FPGA designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chip and off-chip memory. In this paper, we offer our solutions to both of these challenges. Specifically, 1) we propose a stochastic memory partitioning scheme based on the well-known simulated annealing algorithm. It obtains memory partitioning solutions that promote parallelized memory accesses by exploring large solution space; 2) we augment the proposed DLM architecture with a reconfigure hardware graph that can dynamically compute precedence relationship between memory partitions, thus effectively exploiting algorithmic level memory parallelism on a per-application basis. We evaluate the effectiveness of our approach (A3) against two other DLM architecture synthesizing methods: an algorithmic-centric reconfigurable computing architectures with a single monolithic memory (A1) and the heterogeneous distributed architectures synthesized according to [1] (A2). To make our comparison fair, in all three architectures, the data path remains the same while local memory architecture differs. For each of ten benchmark applications from SPEC2006 and MiBench [2], we break down the performance benefit of using A3 into two parts: the portion due to stochastic local memory partitioning and the portion due to the dynamic graph-based memory arbitration. All experiments have been conducted with a V

关键词： Random access memory Field programmable gate arrays Computer architecture Heuristic algorithms Hardware Partitioning algorithms parallel processing

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Proof of Clustering: an efficient and reliable blockchain-based clustering framework

Proof of Clustering: an efficient and reliable blockchain-ba...

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IEEE/ACM international symposium on Big Data Computing (BDC)

作者： Yamina Khenfouci Yacine Challal Laboratoire des Méthodes de Conception de Systèmes (LMCS) Ecole Nationale Supérieure d’Informatique (ESI) Algiers Algeria College of Computing and IT University of Doha for Science and Technology Doha Qatar

ISBN: (数字)9798350367300

ISBN: (纸本)9798350367317

We propose a novel blockchain-based collaborative clustering framework, designed to enhance the efficiency and reliability of data clustering by decentralizing the clustering process across multiple nodes within the blockchain network. The system incorporates a consensus mechanism called Proof of Clustering to achieve the accuracy and consistency of clustering. This results thereby in ensuring confidence and reliability of the final clusters and prevents any breaches or corruption. To improve the performance of clustering process in the decentralized blockchain environment, data parallelism is employed. Through extensive experimentation and performance evaluation, we demonstrate the effectiveness and efficiency of proof of clustering consensus in various scenarios. Comparative studies with traditional centralized and distributed clustering methods showcase the superiority of our proposed solution by in terms of computational speed and resource utilization. PoC improves the Silhouette Score by 5.05% and reduces the Davies-Bouldin Index by 22.93%, indicating better cluster cohesion and separation in the PoC framework.

关键词： Performance evaluation Data analysis Accuracy Collaboration Machine learning parallel processing Reliability engineering Consensus protocol Indexes Resource management

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Supporting systolic and memory communication in iWarp

Supporting systolic and memory communication in iWarp

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Annual international symposium on Computer Architecture, ISCA

作者： S. Borkar R. Cohn G. Cox T. Gross H.T. Kung M. Lam M. Levine B. Moore W. Moore C. Peterson J. Susman J. Sutton J. Urbanski J. Webb School of Computer Science Carnegie Mellon University Pittsburgh PA USA Intel Corporation Hillsboro OR USA

The iWarp communication system supports two widely used interprocessor communication styles: memory communication and systolic communication. A description is given of the rationale, architecture, and implementation for the iWarp communication system. Memory communication is flexible and well suited for general computing, whereas systolic communication is efficient and well suited for speed-critical applications. The iWarp design is made possible by two important innovations in communication: (1) program access to communication and (2) logical channels. The former allows programs to access data as they are transmitted and to redirect portions of messages to different destinations efficiently. The latter increases the connectivity between the processors and guarantees communication bandwidth for classes of messages. These innovations have provided a focus for the iWarp architecture. The result is a communication system that provides a total bandwidth of 320 MBytes/sec and that is integrated on a single VLSI component with a 20 MFLOPS plus 20 MIPS long instruction work computation engine.< >

关键词： Computer architecture Message passing Technological innovation Bandwidth Computer aided instruction Engines parallel processing Concurrent computing distributed computing Wire

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A Fast Adversarial Sample Detection Approach for Industrial Internet-of-Things applications

A Fast Adversarial Sample Detection Approach for Industrial ...

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international Workshop on Quality of Service

作者： Shigeng Zhang Yudong Li Shuxin Chen Xuan Li Jian Zhang School of Computer Science and Engineering Central South University College of Computer Science and Electronic Engineering Hunan University The Science and Technology on Parallel and Distributed Processing Laboratory (PDL) China

Adversarial attacks reveal the inherent vulnerability of deep neural networks, which face serious security issues for their security. Among them, the attack against the Deep Neural Network (DNN) application used in the Industrial Internet of Things (IIoT) is a key area in adversarial attacks. Adversarial examples generated by attackers by adding human-undetectable interference to legitimate examples may cause models to make wrong decision results, resulting in serious accidents. Many detection technologies have been proposed to mitigate the harm of adversarial examples to neural networks, among which the methods based on the difference of feature attribution between normal examples and adversarial examples show state-of-the-art detection performance, but they suffer from detection efficiency. In this work, we focus on improving the detection efficiency of the feature-attribution-based detection methods. We observe that there is still a significant difference in the feature attribution distribution of a normal image and an adversarial image even only some pixels in the image are processed, which can be verified by utilizing the Kolmogorov-Smirnov test. Based on this observation, we first adopt a variety of strategies to sample partial pixels in an image and then utilize the selected pixels to train a feature-attribution-based detector for detecting adversarial examples. Extensive experiments conducted on four datasets (MNIST, CIFAR-10, SVHN, CIFAR-100) against various attacks proved that the detection efficiency of the accelerated detection method is improved (for example, the average execution time was increased by 8.7 times on CIFAR-10) while the detection performance maintains state-of-the-art.

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The Aria-S1-Gunw: The ARIA Sentinel-1 Geocoded Unwrapped Phase Product for Open Insar Science and Disaster Response

The Aria-S1-Gunw: The ARIA Sentinel-1 Geocoded Unwrapped Pha...

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IEEE international symposium on Geoscience and Remote Sensing (IGARSS)

作者： David Bekaert Nicholas Arena M Grace Bato Brett Buzzanga Marin Govorcin Emre Havazli Kirk Hogenson Hook Hua Andrew Johnston Mohammed Karim Joseph H. Kennedy Zhong Lu Charlie Z. Marshak Franz Meyer Susan Owen Simran Sangha Gregory Short Jiahui Wang Robert Zinke Jet Propulsion Laboratory California Institute of Technology Pasadena CA USA Alaska Satellite Facility NASA Distributed Active Archive Center Fairbanks AK USA Geophysical Institute University of Alaska Fairbanks Fairbanks AK USA Department of Earth Sciences Southern Methodist University Dallas TX USA

NASA has committed to open-source science that enables Earth observation data transparency, inclusivity, accessibility, and reproducibility – all fundamental to the pace and quality of scientific progress. We have embraced this vision by producing standard InSAR science products that are freely available to the public through NASA Data Active Archive Centers (DAACs) and are generated using state-of-the-art open-source and openly-developed methods. The Advanced Rapid Image Analysis (ARIA) project’s Sentinel-1 Geocoded Unwrapped Phase product (ARIA-S1-GUNW) is a 90 meter InSAR product that spans major, land-based fault systems, the US Coasts, and active volcanic regions through the complete Sentinel-1 record. The products enable the measurement of centimeter-scale surface displacement with applications across the solid earth, hydrology, and sea-level disciplines. The ARIA-S1-GUNW also enables rapid response mapping of surface motion after earthquakes, landslides, and subsidence. The ARIA-S1-GUNW products are freely available through the Alaska Satellite Facility (ASF) DAAC. In the last year, we have successfully grown the archive to over 1.1 million products, a 6 fold increase, through NASA ACCESS by improving our processing workflow and leveraging HyP3, an AWS-based cloud processing environment. We are continuing to partner with researchers to generate more products over relevant areas of scientific interest. All the processing software and cloud infrastructure are open-source to ensure reproducibility and enable other scientists to modify, improve upon, and scale their own cloud workflows for related InSAR analyses. We have, in parallel, developed and supported open-source, well-documented tools to further streamline time-series analysis from the ARIA-S1-GUNW into deformation analysis workflows.

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RLLL: Accurate Relative Localization of RFID Tags with Low Latency

RLLL: Accurate Relative Localization of RFID Tags with Low L...

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international Workshop on Quality of Service

作者： Xuan Liu Quan Yang Shigeng Zhang Bin Xiao The Science and Technology on Parallel and Distributed Processing Laboratory (PDL) P. R. China College of Computer Science and Electronic Engineering Hunan University P. R. China School of Computer Science and Engineering Central South University P. R. China The Hong Kong Polytechnic University Hong Kong

ISBN: (数字)9781728168876

ISBN: (纸本)9781728168883

Radio frequency identification (RFID) has been widely used in many smart applications. In many scenarios, it is essential to know the ordering of a set of RFID tags. For example, to quickly detect misplaced books in smart libraries, we need to know the relative ordering of the tags attached to the books. Although several relative RFID localization algorithms have been proposed, they usually suffer from large localization latency and cannot support applications that require real-time detection of tag (product) positions like automatic manufacturing on an assembly line. Moreover, existing approaches face significant degradation in ordering accuracy when the tags are close to each other. In this paper, we propose RLLL, an accurate Relative Localization algorithm for RFID tags with Low Latency. RLLL reduces localization latency by proposing a novel geometry-based approach to identifying the V-zone in the phase reading sequence of each tag. Moreover, RLLL uses only the data in the V-zone to calculate relative positions of tags and thus avoids the negative effects of low-quality data collected when the tag is far from the antenna. Experimental results with commercial RFID devices show that RLLL achieves an ordering accuracy of higher than 0.986 with latency less than 0.8 seconds even when the tags are spaced only 7 mm from adjacent tags, in which case the state-of-the-art solutions only achieve ordering accuracy of lower than 0.8 with localization latency larger than 3 seconds.

关键词： RFID tags Manufacturing Antenna arrays Quality of service Libraries

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IPDPS 2012博士生论坛会议征文通知

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计算机应用 2011年第A2期31卷 F0002-F0002页

IEEE IPDPS为并行与分布式计算领域之顶级国际会议。IPDPS 2012将于2012年5月21日至25日在上海召开。该会议包括以下部分：IPDPS主会议、附属研讨会（约10个）、特邀演讲、半日短课程和博士生论坛。

关键词：论坛会博士生征文通知分布式计算 IEEE 国际会议

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IPDPS2012博士生论坛会议征文通知

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计算机应用 2011年第10期31卷 F0002-F0002页

IEEEIPDPS为并行与分布式计算领域之顶级国际会议。IPDPS2012将于2012年5月21日至25日在上海召开。该会议包括以下部分：IPDPS主会议、附属研讨会（约10个）、特邀演讲、半日短课程和博士生论坛。

关键词：论坛会博士生征文通知分布式计算国际会议副主席并行

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Connectivity Results of Complete Cubic Networks as Associated with Linearly Many Faults

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JOURNAL OF INTERCONNECTION NETWORKS 2015年第1-2期15卷 1550007-1550007页

作者： Cheng, Eddie Qiu, Ke Shen, Zhizhang Oakland Univ Dept Math & Stat Rochester MI 48309 USA Brock Univ Dept Comp Sci St Catharines ON L2S 3A1 Canada Plymouth State Univ Dept Comp Sci & Technol Plymouth NH 03264 USA

We propose the complete cubic network structure to extend the existing class of hierarchical cubic networks, and establish a general connectivity result which states that the surviving graph of a complete cubic network, when a linear number of vertices are removed, consists of a large (connected) component and a number of smaller components which altogether contain a limited number of vertices. As applications, we characterize several fault-tolerance properties for the complete cubic network, including its restricted connectivity, i.e., the size of a minimum vertex cut such that the degree of every vertex in the surviving graph has a guaranteed lower bound;its cyclic vertex-connectivity, i.e., the size of a minimum vertex cut such that at least two components in the surviving graph contain a cycle;its component connectivity, i.e., the size of a minimum vertex cut whose removal leads to a certain number of components in its surviving graph;and its conditional diagnosability, i.e., the maximum number of faulty vertices that can be detected via a self-diagnostic process, in terms of the common Comparison Diagnosis model.

关键词： Complete cubic network hierarchical cubic network fault-tolerance property graph connectivity parallel and distributed processing

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