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检索条件"任意字段=International Symposium on Software Engineering for Parallel and Distributed Systems"

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Component-based hazard analysis for mechatronic systems

Component-based hazard analysis for mechatronic systems

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2011 14th IEEE international symposium on Object/Component/Service-Oriented Real-Time distributed Computing Workshops, ISORCW 2011

作者： Priesterjahn, Claudia Sondermann-Wölke, Christoph Tichy, Matthias Hölscher, Christian Software Engineering Group Heinz Nixdorf Institute University of Paderborn Paderborn Germany Mechatronics and Dynamics University of Paderborn Paderborn Germany Organic Computing University of Augsburg Augsburg Germany Design and Drive Technology University of Paderborn Paderborn Germany

ISBN: (纸本)9780769543772

One cannot image today's life without mechatronic systems, which have to be developed in a joint effort by teams of mechanical engineers, electrical engineers, control engineers and software engineers. Often these systems are applied in safety critical environments like in cars or aircrafts. This requires systems that function correctly and do not cause hazardous situations. However, random errors due to wear or external influences cannot be completely excluded. Consequently, we have to perform a hazard analysis for the system. Further, the union of four disciplines in one system requires the development and analysis of the system as a whole. We present a component-based hazard analysis that considers the entire mechatronic system including hardware, i.e. mechanical and electrical components, and software components. Our approach considers the physical properties of different types of flow in mechatronic systems. We have identified reusable patterns for the failure behavior which can be generated automatically. This reduces the effort for the developer. As cycles, e.g. control cycles, are an internal part of every mechatronic system our approach is able to handle cycles. The presented approach has been applied to a real-life case study. © 2011 IEEE.

关键词： Engineers

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Virtualization based secure execution and testing framework

Virtualization based secure execution and testing framework

引用

IASTED international Conference on parallel and distributed Computing and systems, PDCS 2011

作者： Kotikela, Srujan Das Nimgaonkar, Satyajeet Gomathisankaran, Mahadevan Computer Science and Engineering University of North Texas Denton TX United States

ISBN: (纸本)9780889869073

Computer security aims at protecting confidentiality, integrity, and availability of sensitive information that are processed, used, or stored by computing systems. Computer scientists working in the field of computer security have successfully designed and developed software and hardware mechanisms to provide security in modern day computing devices. As compared to hardware security mechanisms, software-only security mechanisms are easy to implement and patch. But software-only security mechanisms cannot ensure protection against hardware-based attacks, thus rendering them vulnerable to such attacks. Hardware mechanism such as secure architectures aim to root the trust of the security solution in the hardware architecture. These security architectures typically deploy security mechanisms like encryption/decryption to protect confidentiality and hashing to protect data integrity. Though the security provided by hardware secure architectures is reliably high, they require modifications to the processor micro-architecture. Any changes to the micro-architecture is an extremely costly and time consuming process. Also, testing these hardware secure architectures is difficult as it requires testing the complete system including hardware, software and applications. Recently, virtualization has emerged to be an efficient and cost effective technology that allows emulating hardware mechanisms. It also enables emulating new hardware features in a virtualized environment. This makes the task of testing security architectures efficient and easy. In this paper, we use a virtualization software to build a Virtualization Based Secure Execution and Testing Framework for testing hardware secure architectures. Our framework provides a mechanism to plug-in secure architectures and monitor or test the system behavior by performing attacks on it.

关键词： Virtualization

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Exploiting hierarchical parallelism using UPC

Exploiting hierarchical parallelism using UPC

引用

25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Wang, Lingyuan Merchant, Saumil El-Ghazawi, Tarek Department of Electrical and Computer Engineering George Washington University United States

ISBN: (纸本)9780769543857

High-Performance Computing (HPC) systems are increasingly moving towards an architecture that is deeply hierarchical. However, the execution model with single-level parallelism embodied in legacy parallel programming models falls short in exploiting the multi-level parallelism opportunities in both hardware architectures and applications. This makes the use of richer execution models imperative in order to fully exploit hierarchical parallelism. Partitioned Global Address Space (PGAS) languages such as Unified parallel C (UPC) are growing in popularity because of their ability to provide a globally shared address space with locality awareness. While UPC provides a welcome improvement over message passing libraries, users still program with a single level of parallelism in the context of SPMD. In this paper, we explore two explicit hierarchical programming approaches based on UPC to improve programmability and performance on hierarchical architectures. The first approach orchestrates computations on multiple sets of thread groups;the second approach extends UPC with nested, shared memory multithreading. This paper presents a detailed description of proposed approaches and demonstrates their effectiveness in the context of the NAS parallel Benchmarks and the Unbalanced Tree Search (UTS). Experimental results indicate that the hierarchical model not only provides greater expressive power but also enhances performance;all three benchmarks exceed the performance of the standard UPC implementations after being incrementally enhanced with hierarchical parallelism. © 2011 IEEE.

关键词： Memory architecture

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Proceedings - 2011 IEEE 13th international symposium on High-Assurance systems engineering, HASE 2011

Proceedings - 2011 IEEE 13th International Symposium on High...

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13th IEEE international symposium on High Assurance systems engineering, HASE 2011

ISBN: (纸本)9780769546155

The proceedings contain 57 papers. The topics discussed include: supporting iterative development of robust operation contracts in UML requirements models;improve the effectiveness of test case generation on EFSM via automatic path feasibility analysis;regression testing of component-based software: a systematic practise based on state testing;animating the approach of deriving operational semantics from algebraic semantics for web services;combining goal models, expert elicitation, and probabilistic simulation for qualification of new technology;personal health record system and integration techniques with various electronic medical record systems;conflict detection and lifecycle management for access control in publish/subscribe systems;enumerating software failures to build dependable distributed applications;Monarch: a high-assurance Java-to-Java (J2j) source-code migrator;and a real time window-based local call admission control algorithm for IP networks.

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distributed Theorem Proving for distributed Hybrid systems

Distributed Theorem Proving for Distributed Hybrid Systems

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13th international Conference on Formal engineering Methods

作者： Renshaw, David W. Loos, Sarah M. Platzer, Andre Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA

ISBN: (纸本)9783642245589

distributed hybrid systems present extraordinarily challenging problems for verification. On top of the notorious difficulties associated with distributed systems, they also exhibit continuous dynamics described by quantified differential equations. All serious proofs rely on decision procedures for real arithmetic, which can be extremely expensive. Quantified Differential Dynamic Logic (QdL) has been identified as a promising approach for getting a handle in this domain. QdL has been proved to be complete relative to quantified differential equations. But important questions remain as to how best to translate this theoretical result into practice: how do we succinctly specify a proof search strategy, and how do we control the computational cost? We address the problem of automated theorem proving for distributed hybrid systems. We identify a simple mode of use of QdL that cuts down on the enormous number of choices that it otherwise allows during proof search. We have designed a powerful strategy and tactics language for directing proof search. With these techniques, we have implemented a new automated theorem prover called KeYmaeraD. To overcome the high computational complexity of distributed hybrid systems verification, KeYmaeraD uses a distributed proving backend. We have experimentally observed that calls to the real arithmetic decision procedure can effectively be made in parallel. In this paper, we demonstrate these findings through an extended case study where we prove absence of collisions in a distributed car control system with a varying number of arbitrarily many cars.

关键词： Hybrid systems

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Rectifying orphan components using group-failover in distributed real-time and embedded systems 11

Rectifying orphan components using group-failover in distrib...

引用

Proceedings of the 14th international ACM Sigsoft symposium on Component based software engineering

作者： Tambe, Sumant Gokhale, Aniruddha ISIS Dept. of EECS Vanderbilt University Nashville TN 37235 United States

ISBN: (纸本)9781450307239

Orphan requests are a significant problem for multi-tier distributed systems since they adversely impact system correctness by violating the exactly-once semantics of applications and may waste resources. Orphan requests stem from the failure(s) of non-deterministic components involved in nested invocations of replicated components. Resolving this problem in the context of resource constrained, component-based, distributed real-time and embedded (DRE) systems that form end-to-end task chains is challenging because conventional transaction-based solutions cannot assure real-time properties of the DRE applications. To address these challenges, this paper presents a group-failover protocol that comprises three key capabilities: real-time failure detection and client failover, timely mitigation of orphan requests, and two novel application state consistency strategies to ensure the correctness of DRE systems by maintaining the exactly-once semantics even during failures. Our solution is implemented in the context of the CIAO real-time CORBA Component Model middleware. Empirical evaluations of the group-failover protocol in both fault-free and failure recovery scenarios for DRE task chains of different sizes demonstratesa low overhead and predictable performance. © 2011 ACM.

关键词： Fault tolerance

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Time utility functions for modeling and evaluating resource allocations in a heterogeneous computing system

Time utility functions for modeling and evaluating resource ...

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Briceño, Luis Diego Khemka, Bhavesh Siegel, Howard Jay Maciejewski, Anthony A. Groër, Christopher Koenig, Gregory Okonski, Gene Poole, Steve Colorado State University Department of Electrical and Computer Engineering Fort Collins CO 80523 United States Colorado State University Department of Computer Science Fort Collins CO 80523 United States Oak Ridge National Laboratory Oak Ridge TN 37830 United States Department of Defense Washington DC 20001 United States

ISBN: (纸本)9780769543857

This study considers a heterogeneous computing system and corresponding workload being investigated by the Extreme Scale systems Center (ESSC) at Oak Ridge National Laboratory (ORNL). The ESSC is part of a collaborative effort between the Department of Energy (DOE) and the Department of Defense (DoD) to deliver research, tools, software, and technologies that can be integrated, deployed, and used in both DOE and DoD environments. The heterogeneous system and workload described here are representative of a prototypical computing environment being studied as part of this collaboration. Each task can exhibit a time-varying importance or utility to the overall enterprise. In this system, an arriving task has an associated priority and precedence. The priority is used to describe the importance of a task, and precedence is used to describe how soon the task must be executed. These two metrics are combined to create a utility function curve that indicates how valuable it is for the system to complete a task at any given moment. This research focuses on using time-utility functions to generate a metric that can be used to compare the performance of different resource schedulers in a heterogeneous computing system. The contributions of this paper are: (a) a mathematical model of a heterogeneous computing system where tasks arrive dynamically and need to be assigned based on their priority, precedence, utility characteristic class, and task execution type, (b) the use of priority and precedence to generate time-utility functions that describe the value a task has at any given time, (c) the derivation of a metric based on the total utility gained from completing tasks to measure the performance of the computing environment, and (d) a comparison of the performance of resource allocation heuristics in this environment. © 2011 IEEE.

关键词： Resource allocation

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Secure fragment allocation in a distributed storage system with heterogeneous vulnerabilities

Secure fragment allocation in a distributed storage system w...

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IEEE international Conference on Networking, Architecture and Storage

作者： Tian, Yun Yin, Shu Xie, Jiong Zhang, Ji Qin, Xiao Alghamdi, Mohammed I. Qiu, Meikang Yang, Yiming Department of Computer Science and Software Engineering Auburn University Auburn AL 36849-5347 United States Al-Baha University Al-Baha City Saudi Arabia Department of Electrical and Computer Engineering University of Kentucky Lexington KY United States Intel Corporation NM 87124 United States

ISBN: (纸本)9780769545097

There is a growing demand for large-scale distributed storage systems to support resource sharing and fault tolerance. Although heterogeneity issues of distributed systems have been widely investigated, little attention has yet been paid to security solutions designed for distributed storage systems with heterogeneous vulnerabilities. This fact motivates us to investigate a fragment allocation scheme called S-FAS to improve security of a distributed system where storage sites have a wide variety of vulnerabilities. In the S-FAS approach, we integrate file fragmentation with the secret sharing technique in a distributed storage system with heterogeneous vulnerabilities. Storage sites in a distributed systems are classified into a variety of different server types based on vulnerability characteristics. Given a file and a distributed system, S-FAS allocates fragments of the file to as many different types of nodes as possible in the system. Data confidentiality is preserved because fragments of a file are allocated to multiple storage nodes. We develop storage assurance and dynamic assurance models to evaluate the quality of security offered by S-FAS. Analysis results show that fragment allocations made by S-FAS lead to enhanced security because of the consideration of heterogeneous vulnerabilities in distributed storage systems. © 2011 IEEE.

关键词： Fault tolerance

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GPU accelerating for rapid multi-core cache simulation

GPU accelerating for rapid multi-core cache simulation

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25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Han, Wan Xiang, Long Gao, Xiaopeng Yi, Li State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing China

ISBN: (纸本)9780769543857

To find the best memory system for emerging workloads, traces are obtained during application's execution, then caches with different configurations are simulated using these traces. Since program traces can be several gigabytes, simulation of cache performance is a time consuming process. Compute unified device architecture (CUDA) is a software development platform which enables programmers to accelerate the general-purpose applications on the graphics processing unit (GPU). This paper presents a real time multi-core cache simulator, which was built based on the Pin tool to get the memory reference;and fast method for multi-core cache simulation using the CUDA-enabled GPU. The proposed method is accelerated by the following techniques: execution parallelism exploration;memory latency hiding;a novel trace compression methodology. We describe how these techniques can be incorporated into CUDA code. Experimental results show that the hybrid parallel method of time-partitioning combines with set-partitioning presented here is 11.10× speedup compared to the CPU serial simulation algorithm. The present simulator can characterize cache performance of single-threaded or multi-threaded workloads at the speeds of 6-15 MIPS. It can simulates 6 cache configurations within one single pass at this speeds compared to CMP$im, which can only simulate one cache configuration each simulation pass at the speeds of 4-10 MIPS. © 2011 IEEE.

关键词： Graphics processing unit

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CAR based safety model in automotive software engineering

CAR based safety model in automotive software engineering

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作者： Chandrasekaran, S. Vijaya Raman, P. Vijayravikumaran, R.S. Department of Information Technology Rajalakshmi Engineering College Anna University of Technology Chennai TamilNadu India Department of Information Technology Jeppiaar Engineering College Anna University of Technology Chennai TamilNadu India Department of Information Technology Valliammai Engineering College Anna University of Technology Chennai TamilNadu India

ISBN: (纸本)9789604742776

The objective of the paper is to propose a design for safety model in automotive software architecture focusing the context awareness features, user actions and unexpected reaction from the environment. The safety aspect in the design and development of automotive software is considered in the system level and also in the detailed software component level. The safety feature proposed in the work is achieved through a V-W software development model and a context-action-reaction safety logic is used which is satisfied using sequent calculus. The hierarchical object oriented design (HOOD) methodology is adopted in the architecture of safe software. The safety due to functionality and behavior of the critical modules like airbag control and tire pressure monitoring are considered in the work and implemented through interacting finite state machines (FSM) as per the existing system and software safety standards. The software safety based on the operational context, user actions and the system reactions in the automotive applications are considered.

关键词： Application programs

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