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检索条件"任意字段=International Symposium on Software Engineering for Parallel and Distributed Systems"

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An industrial application of model checking to a vessel control system

An industrial application of model checking to a vessel cont...

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2011 6th IEEE international symposium on Electronic Design, Test and Application, DELTA 2011

作者： Keating, Daniel McInnes, Allan Hayes, Michael Electrical and Computer Engineering University of Canterbury New Zealand

ISBN: (纸本)9780769543062

Model checking allows an abstracted finite state model of a system to be developed and a set of mathematically defined correctness properties, based on the design specifications, to be defined. The model checker performs an exhaustive state space search of the model, checking the correctness properties hold at each step. This paper describes how model checking has been applied to find and correct problems in the software design of a distributed vessel control system currently under development at a control systems specialist in New Zealand. © 2011 IEEE.

关键词： Model checking

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Translating chapel to use FREERIDE: A case study in using an HPC language for data-intensive computing

Translating chapel to use FREERIDE: A case study in using an...

引用

25th IEEE international parallel and distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Ren, Bin Agrawal, Gagan Chamberlain, Brad Deitz, Steve Department of Computer Science and Engineering Ohio State University Columbus OH 43210 United States Cray Inc. 901 Fifth Avenue Seattle WA 98164 United States

ISBN: (纸本)9780769543857

In the last few years, the growing significance of data-intensive computing has been closely tied to the emergence and popularity of new programming paradigms for this class of applications, including Map-Reduce, and new high-level languages for data-intensive computing. The ultimate goal of these efforts in data-intensive computing has been to achieve parallelism with as little effort as possible, while supporting high efficiency and scalability. While these are also the goals that the parallel language/compiler community has tried meeting for the past several decades, the development of languages and programming systems for data-intensive computing has largely been in isolation to the developments in general parallel programming. Such independent developments in the two areas, i.e., dataintensive computing and high productivity languages lead to the following questions: I) Are HPC languages suitable for expressing data-intensive computations? and if so, II.a) What are the issues in using them for effective parallel programming? or, if not, II.b) What characteristics of data-intensive computations force the need for separate language support?. This paper takes a case study to address these questions. Particularly, we study the suitability of Chapel for expressing dataintensive computations. We also examine compilation techniques required for directly invoking a data-intensive middleware from Chapel's compilation system. The data-intensive middleware we use in this effort is FREERIDE that has been developed at Ohio State. We show how certain transformations can enable efficient invocation of the FREERIDE functions from the Chapel compiler. Our experiments show that after certain optimizations, the performance of the version of Chapel compiler that invokes FREERIDE functions is quite comparable to the performance of hand-written data-intensive applications. © 2011 IEEE.

关键词： parallel programming

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High performance content-based matching using GPUs 11

High performance content-based matching using GPUs

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Proceedings of the 5th ACM international conference on distributed event-based system

作者： Margara, Alessandro Cugola, Gianpaolo Dip. di Elettronica e Informazione Politecnico di Milano Milano Italy

ISBN: (纸本)9781450309059

Matching incoming event notifications against received subscriptions is a fundamental part of every publish-subscribe infrastructure. In the case of content-based systems this is a fairly complex and time consuming task, whose performance impacts that of the entire system. In the past, several algorithms have been proposed for efficient content-based event matching. While they differ in most aspects, they have in common the fact of being conceived to run on conventional, sequential hardware. On the other hand, modern Graphical Processing Units (GPUs) offer off-the-shelf, highly parallel hardware, at a reasonable cost. Unfortunately, GPUs introduce a totally new model of computation, which re- quires algorithms to be fully re-designed. In this paper, we describe a new content-based matching algorithm designed to run efficiently on CUDA, a widespread architecture for general purpose programming on GPUs. A detailed comparison with SFF, the matching algorithm of Siena, known for its efficiency, demonstrates how the use of GPUs can bring impressive speedups in content-based matching. At the same time, this analysis demonstrates the peculiar aspects of CUDA programming that mostly impact performance. © 2011 ACM.

关键词： parallel architectures

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ICPE'11 - Proceedings of the 2nd Joint WOSP/SIPEW international Conference on Performance engineering

ICPE'11 - Proceedings of the 2nd Joint WOSP/SIPEW Internatio...

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2nd Joint WOSP/SIPEW international Conference on Performance engineering, ICPE 2011

ISBN: (纸本)9781450305198

The proceedings contain 59 papers. The topics discussed include: proprietary code to non-proprietary benchmarks: synthesis techniques for scalable benchmarks;performance analysis of domain specific visual models;performance modeling in MapReduce environments: challenges and opportunities;computing first passage time distributions in stochastic well-formed nets;detection and solution of software performance antipatterns in Palladio architectural models;an approach for scalability-bottleneck solution: identification and elimination of scalability bottlenecks in a DBMS;experience building non-functional requirement models of a complex industrial architecture;relative roles of instruction count and cycles per instruction in WCET estimation;an automatic trace based performance evaluation model building for parallel distributed systems;and real-world performance modeling of enterprise service oriented architectures: delivering business value with complexity and constraints.

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Communication-aware design space exploration for efficient run-time MPSoC management

Communication-aware design space exploration for efficient r...

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2011 4th international symposium on parallel Architectures, Algorithms and Programming, PAAP 2011

作者： Singh, Amit Kumar Kumar, Akash Wu, Jigang Srikanthan, Thambipillai School of Computer Engineering Nanyang Technological University Singapore Singapore Department of Electrical and Computer Engineering National University of Singapore Singapore Singapore School of Computer Science and Software Tianjin Polytechnic University Tianjin China

ISBN: (纸本)9780769545752

Real-time multi-media applications are increasingly mapped on modern embedded systems based on Multiprocessor systems-on-Chip (MPSoCs). Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisfy their performance constraints. Exploring all the mappings, i.e. tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time that cannot handle dynamism in applications and resources' status. A run-time mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communication-aware design space exploration techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results. © 2011 IEEE.

关键词： Mapping

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Automatic compilation of C applications for FPGA-based hardware acceleration

Automatic compilation of C applications for FPGA-based hardw...

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2011 4th international symposium on parallel Architectures, Algorithms and Programming, PAAP 2011

作者： Chuong, Lieu My Aung, Yan Lin Lam, Siew-Kei Srikanthan, Thambipillai Soon, Lim Chai PixelMetrix Corporation Singapore Singapore Centre for High Performance Embedded Systems Nanyang Technological University Singapore Singapore School of Engineering Republic Polytechnic Singapore Singapore

ISBN: (纸本)9780769545752

Advancement in design tools is necessary to bridge the widening productivity gap between hardware design and software development in state-of-the-art Field Programmable Gate Arrays (FPGA). We present a design exploration framework that automatically compiles C applications to realize efficient custom coprocessor structures for hardware acceleration on the reconfigurable logic. We show that the proposed design exploration framework can automatically generate Register Transfer Level (RTL) codes from C-functions that outperform the commercial Altera C2H RTL generator by about 40% in terms of average area-time product. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A multi-scale agent-based distributed simulation framework for groundwater pollution management 11

A multi-scale agent-based distributed simulation framework f...

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15th IEEE/ACM international symposium on distributed Simulation and Real Time Applications, DS-RT 2011

作者： Schmidt, Susanne I. Picioreanu, Cristian Craenen, Bart Mackay, Rae Kreft, Jan-Ulrich Theodoropoulos, Georgios Centre for Systems Biology University of Birmingham United Kingdom Department of Biochemical Engineering Delft University of Technology Delft Netherlands School of Computer Science University of Birmingham United Kingdom Geography Earth and Environmental Sciences University of Birmingham United Kingdom IBM Research Dublin Research Lab. Ireland

ISBN: (纸本)9780769545530

Groundwater is like dark matter - we know very little apart from the fact that it is hugely important. Given the scarcity of data, mathematical modelling can come to the rescue but existing groundwater models are mainly restricted to simulate the transport and degradation of contaminants on the scale of whole contaminated field sites by averaging out the effect of spatial heterogeneity on the availability of the pollutant to the degrading organisms. These coarse-scale mean-field models therefore tend to rely on fitting to data rather than being predictive. Also, they are less suited to incorporate spatial variability and non-linear kinetics and feedbacks. We propose to solve the two mutually exacerbating problems of environmental patchiness and data scarcity by developing a flexible and robust distributed simulation framework that uses an ensemble of small scale simulations running on different processors/computers to scale-up, i.e. to feed the effect of small-scale patchiness into a concurrent site-scale simulation of the dynamics of groundwater pollutant degradation. Our scaling approach solves problem #1 by simulating dynamics also on the small scale where some of the patchiness resides, and problem #2 by enabling rigorous validation of our small-scale model and scaling approach with laboratory data, which are high quality at low cost. © 2011 IEEE.

关键词： Groundwater

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Achieving Target MTTF by Duplicating Reliability-Critical Components in High Performance Computing systems

Achieving Target MTTF by Duplicating Reliability-Critical Co...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Nithin Nakka Alok Choudhary Gary Grider John Bent James Nunez Satsangat Khalsa Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Electrical Engineering and Computer Science Northwestern University Evanston IL USA Los Alamos National Laboratories Albuquerque NM USA

Mean Time To failure, MTTF, is a commonly accepted metric for reliability. In this paper we present a novel approach to achieve the desired MTTF with minimum redundancy. We analyze the failure behavior of large scale systems using failure logs collected by Los Alamos National Laboratory. We analyze the root cause of failures and present a choice of specific hardware and software components to be made fault-tolerant, through duplication, to achieve target MTTF at minimum expense. Not all components show similar failure behavior in the systems. Our objective, therefore, was to arrive at an ordering of components to be incrementally selected for protection to achieve a target MTTF. We propose a model for MTTF for tolerating failures in a specific component, system-wide, and order components according to the coverage provided. systems grouped based on hardware configuration showed similar improvements in MTTF when different components in them were targeted for fault-tolerance.

关键词： Fault tolerant systems Maintenance engineering Hardware Redundancy software

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Multifrontal factorization of sparse SPD matrices on GPUs

Multifrontal factorization of sparse SPD matrices on GPUs

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

作者： George, Thomas Saxena, Vaibhav Gupta, Anshul Singh, Amik Choudhury, Anamitra R. High Performance Computing Group IBM Research India New Delhi 110070 India Department of Mathematical Sciences IBM T.J. Watson Research Center Yorktown Heights NY United States Department of Electronics and Computer Engineering IIT Roorkee India

ISBN: (纸本)9780769543857

Solving large sparse linear systems is often the most computationally intensive component of many scientific computing applications. In the past, sparse multifrontal direct factorization has been shown to scale to thousands of processors on dedicated supercomputers resulting in a substantial reduction in computational time. In recent years, an alternative computing paradigm based on GPUs has gained prominence, primarily due to its affordability, power-efficiency, and the potential to achieve significant speedup relative to desktop performance on regular and structured parallel applications. However, sparse matrix factorization on GPUs has not been explored sufficiently due to the complexity involved in an efficient implementation and concerns of low GPU utilization. In this paper, we present an adaptive hybrid approach for accelerating sparse multifrontal factorization based on a judicious exploitation of the processing power of the host CPU and GPU. We present four different policies for distributing and scheduling the workload between the host CPU and the GPU, and propose a mechanism for a runtime selection of the appropriate policy for each step of sparse Cholesky factorization. This mechanism relies on auto-tuning based on modeling the best policy predictor as a parametric classifier. We estimate the classifier parameters from the available empirical computation time data such that the expected computation time is minimized. This approach is readily adaptable for using the current or an extended set of policies for different CPU-GPU combinations as well as for different combinations of dense kernels for both the CPU and the GPU. © 2011 IEEE.

关键词： Factorization

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A novel power management for CMP systems in data-intensive environment

A novel power management for CMP systems in data-intensive e...

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

作者： Shang, Pengju Wang, Jun Computer Engineering and Computer Science Dept. University of Central Florida Orlando FL United States

ISBN: (纸本)9780769543857

The emerging data-intensive applications of today are comprised of non-uniform CPU and I/O intensive workloads, thus imposing a requirement to consider both CPU and I/O effects in the power management strategies. Only scaling down the processor's frequency based on its busy/idle ratio cannot fully exploit opportunities of saving power. Our experiments show that besides the busy and idle status, each processor may also have I/O wait phases waiting for I/O operations to complete. During this period, the completion time is decided by the I/O subsystem rather than the CPU thus scaling the processor to a lower frequency will not affect the performance but save more power. In addition, the CPU's reaction to the I/O operations may be significantly affected by several factors, such as I/O type (sync or unsync), instruction/job level parallelism, it cannot be accurately modeled via physics laws like mechanical or chemical systems. In this paper, we propose a novel power management scheme called MAR (modeless, adaptive, rule-based) in multiprocessor systems to minimize the CPU power consumption under performance constraints. By using richer feedback factors, e.g. the I/O wait, MAR is able to accurately describe the relationships among core frequencies, performance and power consumption. We adopt a modeless control model to reduce the complexity of system modeling. MAR is designed for CMP (Chip Multi Processor) systems by employing multi-input/multi-output (MIMO) theory and per core level DVFS (Dynamic Voltage and Frequency Scaling). Our extensive experiments on a physical test bed demonstrate that, for the SPEC benchmark and data-intensive (TPC-C) benchmark, the efficiency of MAR is 93.6-96.2% accurate to the ideal power saving strategy calculated off-line. Compared with baseline solutions, MAR could save 22.5-32.5% more power while keeping the comparable performance loss of about 1.8-2.9%. In addition, simulation results show the efficiency of our design for various CMP conf

关键词： Electric power utilization

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