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Achieving Target MTTF by Duplicating Reliability-Critical Components in High Performance Computing systems

Achieving Target MTTF by Duplicating Reliability-Critical Co...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Nithin Nakka Alok Choudhary Gary Grider John Bent James Nunez Satsangat Khalsa Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Electrical Engineering and Computer Science Northwestern University Evanston IL USA Los Alamos National Laboratories Albuquerque NM USA

Mean Time To failure, MTTF, is a commonly accepted metric for reliability. In this paper we present a novel approach to achieve the desired MTTF with minimum redundancy. We analyze the failure behavior of large scale systems using failure logs collected by Los Alamos National Laboratory. We analyze the root cause of failures and present a choice of specific hardware and software components to be made fault-tolerant, through duplication, to achieve target MTTF at minimum expense. Not all components show similar failure behavior in the systems. Our objective, therefore, was to arrive at an ordering of components to be incrementally selected for protection to achieve a target MTTF. We propose a model for MTTF for tolerating failures in a specific component, system-wide, and order components according to the coverage provided. systems grouped based on hardware configuration showed similar improvements in MTTF when different components in them were targeted for fault-tolerance.

关键词： Fault tolerant systems Maintenance engineering Hardware Redundancy software

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Multifrontal factorization of sparse SPD matrices on GPUs

Multifrontal factorization of sparse SPD matrices on GPUs

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

作者： George, Thomas Saxena, Vaibhav Gupta, Anshul Singh, Amik Choudhury, Anamitra R. High Performance Computing Group IBM Research India New Delhi 110070 India Department of Mathematical Sciences IBM T.J. Watson Research Center Yorktown Heights NY United States Department of Electronics and Computer Engineering IIT Roorkee India

ISBN: (纸本)9780769543857

Solving large sparse linear systems is often the most computationally intensive component of many scientific computing applications. In the past, sparse multifrontal direct factorization has been shown to scale to thousands of processors on dedicated supercomputers resulting in a substantial reduction in computational time. In recent years, an alternative computing paradigm based on GPUs has gained prominence, primarily due to its affordability, power-efficiency, and the potential to achieve significant speedup relative to desktop performance on regular and structured parallel applications. However, sparse matrix factorization on GPUs has not been explored sufficiently due to the complexity involved in an efficient implementation and concerns of low GPU utilization. In this paper, we present an adaptive hybrid approach for accelerating sparse multifrontal factorization based on a judicious exploitation of the processing power of the host CPU and GPU. We present four different policies for distributing and scheduling the workload between the host CPU and the GPU, and propose a mechanism for a runtime selection of the appropriate policy for each step of sparse Cholesky factorization. This mechanism relies on auto-tuning based on modeling the best policy predictor as a parametric classifier. We estimate the classifier parameters from the available empirical computation time data such that the expected computation time is minimized. This approach is readily adaptable for using the current or an extended set of policies for different CPU-GPU combinations as well as for different combinations of dense kernels for both the CPU and the GPU. © 2011 IEEE.

关键词： Factorization

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A novel power management for CMP systems in data-intensive environment

A novel power management for CMP systems in data-intensive e...

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25th IEEE international parallel and distributed Processing symposium, IPDPS 2011

作者： Shang, Pengju Wang, Jun Computer Engineering and Computer Science Dept. University of Central Florida Orlando FL United States

ISBN: (纸本)9780769543857

The emerging data-intensive applications of today are comprised of non-uniform CPU and I/O intensive workloads, thus imposing a requirement to consider both CPU and I/O effects in the power management strategies. Only scaling down the processor's frequency based on its busy/idle ratio cannot fully exploit opportunities of saving power. Our experiments show that besides the busy and idle status, each processor may also have I/O wait phases waiting for I/O operations to complete. During this period, the completion time is decided by the I/O subsystem rather than the CPU thus scaling the processor to a lower frequency will not affect the performance but save more power. In addition, the CPU's reaction to the I/O operations may be significantly affected by several factors, such as I/O type (sync or unsync), instruction/job level parallelism, it cannot be accurately modeled via physics laws like mechanical or chemical systems. In this paper, we propose a novel power management scheme called MAR (modeless, adaptive, rule-based) in multiprocessor systems to minimize the CPU power consumption under performance constraints. By using richer feedback factors, e.g. the I/O wait, MAR is able to accurately describe the relationships among core frequencies, performance and power consumption. We adopt a modeless control model to reduce the complexity of system modeling. MAR is designed for CMP (Chip Multi Processor) systems by employing multi-input/multi-output (MIMO) theory and per core level DVFS (Dynamic Voltage and Frequency Scaling). Our extensive experiments on a physical test bed demonstrate that, for the SPEC benchmark and data-intensive (TPC-C) benchmark, the efficiency of MAR is 93.6-96.2% accurate to the ideal power saving strategy calculated off-line. Compared with baseline solutions, MAR could save 22.5-32.5% more power while keeping the comparable performance loss of about 1.8-2.9%. In addition, simulation results show the efficiency of our design for various CMP conf

关键词： Electric power utilization

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An On-line distributed Induction Motor Monitoring System Based-on ARM and CAN Bus

An On-line Distributed Induction Motor Monitoring System Bas...

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international Conference on parallel Computing in Electrical engineering (PARLEC)

作者： Chenhui Wang Yukun Liu Liwei Guo Yong Yue Carsten Maple College of Electrical Engineering and Information Hebei University of Science and Technology Shijiazhuang Hebei China College of Information Science and Engineering Hebei University of Science and Technology Shijiazhuang Hebei China Faculty of Creative Arts Technologies and Science University of Bedfordshire Bedfordshire UK

This paper presents an on-line distributed induction motor monitoring system based-on the ARM (Advanced RISC Machines), which is integrated with the embedded and CAN (Controller Area Network) bus technologies. The hardware structure of the system with the ARM microprocessor S3C2410X and CAN bus controller MCP2510 is introduced, the accomplishment of software of motor on-line monitoring system is also described. Compared to the complicated construction and low integration of traditional motor testing systems, this system has a reasonable structure with less external expansion units, and can carry out data transmission in real time, effectively, and with lower power cost and more reliability.

关键词： Induction motors Monitoring software Microprocessors Hardware Driver circuits Real time systems

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Product model derivation by model transformation in software product lines

Product model derivation by model transformation in software...

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2011 14th IEEE international symposium on Object/Component/Service-Oriented Real-Time distributed Computing Workshops, ISORCW 2011

作者： Tawhid, Rasha Petriu, Dorina C. School of Computer Science Carleton University Ottawa ON Canada Dept. of Systems and Computer Engineering Carleton University Ottawa ON Canada

ISBN: (纸本)9780769543772

Product derivation is an essential part of the software Product Line (SPL) development process. The paperproposes a model transformation for deriving automatically a UML model of a specific product from the UML model of a product line. This work is a part of a larger project aiming to integrate performance analysis in the SPL model-driven development. The SPL source model is expressed in UML extended with two separate profiles: a "product line" profile from literature for specifying the commonality and variability between products, and the MARTE profile recently standardized by OMG for performance annotations. The automatic derivation of a concrete product model based on a given feature configuration is enabled through the mapping between features from the feature model and their realizations in the design model. The paper proposes an efficient mapping technique that aims to minimize the amount of explicit feature annotations in the UML design model of SPL. Implicit feature mapping is inferred during product derivation from the relationships between annotated and non-annotated model elements as defined in the UML metamodel and well formedness rules. The transformation is realized in the Atlas Transformation Language (ATL) and illustrated with an ecommerce case study that models structural and behavioural SPL views. © 2011 IEEE.

关键词： Mapping

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Implementing High Performance Remote Method Invocation in CCA

Implementing High Performance Remote Method Invocation in CC...

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IEEE international Conference on Cluster Computing (CLUSTER)

作者： Yin, Jian Agarwal, Khushbu Krishnan, Manoj Chavarria-Miranda, Daniel Gorton, Ian Epperly, Tom Pacific NW Natl Lab POB 999 Richland WA 99352 USA Lawrence Livermore Natl Lab Livermore CA 94551 USA

ISBN: (纸本)9780769545165

We report our effort in engineering a high performance remote method invocation (RMI) mechanism for the Common Component Architecture (CCA). This mechanism provides a highly efficient and easy-to-use mechanism for distributed computing in CCA, enabling CCA applications to effectively leverage parallel systems to accelerate computations. This work is built on the previous work of Babel RMI. Babel is a high performance language interoperability tool that is used in CCA for scientific application writers to share, reuse, and compose applications from software components written in different programming languages. Babel provides a transparent and flexible RMI framework for distributed computing. However, the existing Babel RMI implementation is built on top of TCP and does not provide the level of performance required to distribute fine-grained tasks. We observed that the main reason the TCP based RMI does not perform well is because it does not utilize the high performance interconnect hardware on a cluster efficiently. We have implemented a high performance RMI protocol, HPCRMI. HPCRMI achieves low latency by building on top of a low-level portable communication library, Aggregated Remote Message Copy Interface (ARMCI), and minimizing communication for each RMI call. Our design allows a RMI operation to be completed by only two RDMA operations. We also aggressively optimize our system to reduce copying. In this paper, we discuss the design and our experimental evaluation of this protocol. Our experimental results show that our protocol can improve RMI performance by an order of magnitude.

关键词： Aggregated Remote Message Copy Interface Babel Common Component Architecture Component architectures distributed computing Hardware High Performance Computing Libraries Programming Protocols Remote Method Invocation software

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DOT: A matrix model for analyzing, optimizing and deploying software for big data analytics in distributed systems

DOT: A matrix model for analyzing, optimizing and deploying ...

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2nd ACM symposium on Cloud Computing, SOCC 2011

作者： Huai, Yin Lee, Rubao Zhang, Simon Xia, Cathy H. Zhang, Xiaodong Department of Computer Science and Engineering Ohio State University United States Department of Computer Science Cornell University United States

ISBN: (纸本)9781450309769

Traditional parallel processing models, such as BSP, are "scale up" based, aiming to achieve high performance by increasing computing power, interconnection network band- width, and memory/storage capacity within dedicated sys- tems, while big data analytics tasks aiming for high through- put demand that large distributed systems "scale out" by continuously adding computing and storage resources through networks. Each one of the "scale up" model and "scale out" model has a different set of performance requirements and system bottlenecks. In this paper, we develop a general model that abstracts critical computation and communica- tion behavior and computation-communication interactions for big data analytics in a scalable and fault-tolerant man- ner. Our model is called DOT, represented by three matri- ces for data sets (D), concurrent data processing operations (O), and data transformations (T), respectively. With the DOT model, any big data analytics job execution in vari- ous software frameworks can be represented by a specific or non-specific number of elementary/composite DOT blocks, each of which performs operations on the data sets, stores intermediate results, makes necessary data transfers, and performs data transformations in the end. The DOT model achieves the goals of scalability and fault-tolerance by en- forcing a data-dependency-free relationship among concur- rent tasks. Under the DOT model, we provide a set of op- timization guidelines, which are framework and implemen- tation independent, and applicable to a wide variety of big data analytics jobs. Finally, we demonstrate the effective- ness of the DOT model through several case studies. Copyright 2011 ACM.

关键词： Scalability

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An ethological motion capture system

An ethological motion capture system

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12th IEEE international symposium on Computational Intelligence and Informatics, CINTI 2011

作者： Devecseri, Viktor Dóka, Antal Molnár, József Tamás, Péter Budapest University of Technology and Economics Department of Mechatronics Optics and Information Engineering Budapest Hungary Eötvös Loránd University Faculty of Sciences Department of Ethology Budapest Hungary

ISBN: (纸本)9781457700453

The motion of living beings can be recorded with motion capture systems. The recorded data can be used to animate virtual characters. There are many methods used by motion capture systems. The paper presents the development of a motion capture system for more than one performer with active optical markers. The performers wear homogenous, illuminating markers attached to each relevant joint. Movements are captured by 6 high speed cameras in order to determine the markers' position in the cameras' image. The cameras operate at 60 fps. The image processing is distributed among multiple computers. Luckily most of the image processing tasks are highly parallel, so the high parallel computational capacity of modern programmable GPUs can be exploited. The main computer calculates the markers' 3D positions after it receives the 2D data from image processing. Each marker needs to be identified, so the markers' 2D and 3D positions are tracked. A hierarchy can be defined between the points in the point cloud, which can be used to determine the bones' hierarchical transformation chain in the characters' skeleton. To achieve satisfying results precise calibration is required. © 2011 IEEE.

关键词： High speed cameras

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A study on educational data clustering approach based on improved particle swarm optimizer

A study on educational data clustering approach based on imp...

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2011 IEEE international symposium on IT in Medicine and Education, ITME 2011

作者： Zheng, Xiangwei Jia, Yuanjiang School of Information Science and Engineering Shandong Normal University Jinan 250014 China Shandong Provincial Key Lab Distributed Computer Software Novel Technology Jinan 250014 China

ISBN: (纸本)9781612847023

More and more clustering approaches are used in educational data mining for too many data are generated by web-based educational systems. To deal with the problem of premature convergence of the traditional K-means algorithm and computational costs, an improved K-means clustering algorithm based cooperative PSO frame is proposed in this paper. Cooperative PSO has been proved effective for large scale and complex problems via a divide-and-conquer strategy by simulating coevolutionary techniques in nature. Therefore, K-means clustering algorithm based cooperative PSO frame is effective in educational data clustering. © 2011 IEEE.

关键词： Data mining

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TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

TMbox: A Flexible and Reconfigurable 16-core Hybrid Transact...

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IEEE 19th Annual international symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Sonmez, Nehir Arcas, Oriol Pflucker, Otto Unsal, Osman S. Cristal, Adrian Hur, Ibrahim Singh, Satnam Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Spanish Natl Res Council Madrid Spain Microsoft Res Cambridge Cambridge England

ISBN: (纸本)9780769543017

In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

关键词： Field programmable gate arrays Hardware MIPS R3000-compatible core MPSoC Multicore processing Proposals Registers software TMbox TinySTM-ASF Virtex-5 FPGA electronic engineering computing field programmable gate arrays flexible 16-core hybrid transactional memory system flexible system logic design multicore design space multicore prototyping multiprocessing systems parallel programming parallel programming reconfigurable 16-core hybrid transactional memory system reconfigurable architectures reconfigurable computing system-on-chip transactional memory

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