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Performance Evaluation of Wireless Sensor Networks for Mobile Sensor Nodes Considering Goodput and Depletion Metrics

Performance Evaluation of Wireless Sensor Networks for Mobil...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Leonard Barolli Tao Yang Gjergji Mino Arjan Durresi Fatos Xhafa Makoto Takizawa Department of Information and Communication Engineering Fukuoka Institute of Technology Fukuoka Japan Comput. Technol. Solution Salem NH USA Department of Computer and Information Science Indiana University-Purdue University Indianapolis Indianapolis IN USA Department of Languages and Informatics Systems Technical University of Catalonia Barcelona Spain Department of Computers and Information Science Seikei University Musashino Tokyo Japan

Sensor networks are a sensing, computing and communication infrastructure that are able to observe and respond to phenomena in the natural environment and in our physical and cyber infrastructure. In this paper, we propose a sensor network with mobile and static sensor nodes set-up for performing tasks like sensing a phenomenon or monitoring a region. We investigate how the sensor network performs in the case when the sensor nodes move. We compare the simulation results for two cases: the sensor network with stationary sensor nodes and multi mobile sensor nodes. The simulation results have shown that for the multi mobile sensors, the good put is unstable. The good put of stationary sensors is better than multi mobile sensors, but the consumed energy of multi mobile sensors is better than stationary sensors.

关键词： Mobile communication Robot sensing systems Wireless sensor networks Simulation Mobile computing Receivers Lattices

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A Case Study of the Interplay between Conflict Management and Version Management in Hardware Transactional Memory systems

A Case Study of the Interplay between Conflict Management an...

引用

international symposium on parallel Architectures, Algorithms and Programming (PAAP)

作者： Zhichao Yan Dan Feng Yujuan Tan Wuhan National Laboratory of Optoelectronics School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

As one of the most potential solution to parallel programming on the future many-core platforms, Transactional Memory (TM) systems have attracted a great deal of attention from both the industry and academic since the first TM was proposed in 1993. Various design and implementation proposals have been proposed to improve the performance while reducing the overheads. Recent investigations of the high-contention and coarse-grained transactional workloads on TMs reveal various pathologies that will offset the performance benefits. In this paper, we analysis the advantages and disadvantages of the existing conflict management and version management schemes, make a case study in the interplay between conflict management and version management in hardware transactional memory systems, to learn its impact on performance and find some interesting appearance that can guide the future design. In particular, apply software runtime environment to support recognize application's dynamic behaviors and resolve transactional conflicts can obtain an average speedup of 11.7% across the 8 applications selected from the STAMP benchmark suite on DynTM, which is regarded as one of the most latest progress in hardware transactional memory systems.

关键词： Pathology Runtime Hardware Memory management Accuracy Maintenance engineering software

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Scheduling of Energy Storage systems with Geographically distributed Renewables

Scheduling of Energy Storage Systems with Geographically Dis...

引用

IEEE international symposium on parallel and distributed Processing with Applications Workshops (ISPAW)

作者： Alberto J. Lamadrid Tim D. Mount Robert J. Thomas Dyson School of Applied Economics and Management Cornell University Ithaca NY USA School of Electrical and Computer Engineering Cornell University Ithaca NY USA

Renewable energy sources (RES) are very likely to continue the upward capacity trend witnessed in the past years. The reasons for adoption are varied and respond to both market pressures, influence of government intervention and a raised awareness of the consequences on the environment of the current generation fleet. The change from dispatch able generation to an environment in which Independent System Operators (ISO's), Regional Transmission Operators (RTO's) and consumers, among others, accommodate the demand to the available generation, requires fundamental changes in the way the system is managed. Also, to better harness the energy from renewable sources, both new methods and technologies need to be adopted, counteracting for the sometimes unpredictable behavior of these sources. This study proposes a method with multi-period optimization to help prescribe the optimal placement and usage of RES and Energy Storage systems (ESS) with full information of the system. Four cases are analyzed in their dispatches, as well as the benefits to the participants in the wholesale market, for a reduced 30-bus network. While the data requirements are high, and the use of a reduced system limits the applications herein proposed, the policy implications from the results obtained provide useful insights into an ongoing debate regarding on how to direct investment in the electrical system.

关键词： Wind forecasting Availability Wind farms Generators Optimization Reactive power

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A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

A Heterogeneous Multicore System on Chip with Run-Time Recon...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： M. Hubner P. Figuli R. Girardey D. Soudris K. Siozios J. Becker Karlsruhe Institute of Technology Germany School of Electrical and Computer Engineering National and Technical University of Athens Greece

System design, especially for low power embedded applications often profit from a heterogeneous target hardware platform. The application can be partitioned into modules with specific requirements e.g. parallelism or performance in relation to the provided hardware blocks on the multicore hardware. The result is an optimized application mapping and a parallel processing with lower power consumption on the different cores on the hardware. This paper presents a heterogeneous platform consisting of a microprocessor and a field programmable gate array (FPGA) connected via a standard AMBA bus. The novelty of this approach is that the FPGA is realized as virtual reconfigurable hardware upon a traditional off the shelf FPGA device. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent to the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform and describes the tool chain for the heterogeneous system on chip.

关键词： Field programmable gate arrays Hardware Computer architecture Routing Microprocessors System-on-a-chip software

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A Study of Key Success Factors for Supply Chain Management System in Semiconductor Industry

A Study of Key Success Factors for Supply Chain Management S...

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ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： Ta-Ping Lu Bang-Ning Hwang Yu-Da Chang Department of Industrial Engineering and Management National Taipei University of Technology Taipei Taiwan Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Graduate Institute of Industrial Engineering and Management National Taipei University of Technology Taipei Taiwan

Developing a supply chain management (SCM) system is costly, but important. However, because of its complicated nature, not many of such projects are considered successful. Few research publications directly relate to key success factors (KSFs) for implementing and operating a SCM system. Motivated by the above, this research proposes two hierarchies of KSFs for SCM system implementation and operation phase respectively in the semiconductor industry by using a two-step approach. First, a literature review indicates the initial hierarchy. The second step includes a focus group approach to finalize the proposed KSF hierarchies by extracting valuable experiences from executives and managers that actively participated in a project, which successfully establish a seamless SCM integration between the world's largest semiconductor foundry manufacturing company and the world's largest assembly and testing company. Finally, this research compared the KSF's between the two phases and made a conclusion. Future project executives may refer the resulting KSF hierarchies as a checklist for SCM system implementation and operation in semiconductor or related industries.

关键词： Supply chain management Supply chains Companies Collaboration Electronics industry Information systems

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Private Cloud System Based on BOINC with Support for parallel and distributed Simulation

Private Cloud System Based on BOINC with Support for Paralle...

引用

IEEE international symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Yihua Wu Jian Cao Minglu Li Shanghai Key Laboratory of Scalable Computing and Systems Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai China

Cloud computing provides an efficient way to expose computing capabilities as sophisticated services that can be accessed remotely. It eliminates the need for organizations to maintain extensive infrastructures. parallel and distributed simulation over cloud will bring us not only the increased productivity and efficiency but also the lower barrier for usage. This paper introduces a private cloud system based on BOINC which supports parallel and distributed simulation. The design idea and implementation method of each component for our system is discussed in detail.

关键词： Computational modeling Monitoring Cloud computing Load modeling Servers Probes

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Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration

Automatic Compilation of C Applications for FPGA-Based Hardw...

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international symposium on parallel Architectures, Algorithms and Programming (PAAP)

作者： Lieu My Chuong Yan Lin Aung Siew-Kei Lam Thambipillai Srikanthan Lim Chai Soon Pixel Metrix Corporation Singapore Centre of High Performance Embedded Systems Nanyang Technological University Singapore School of Engineering Republic Polytechnic Singapore

Advancement in design tools is necessary to bridge the widening productivity gap between hardware design and software development in state-of-the-art Field Programmable Gate Arrays (FPGA). We present a design exploration framework that automatically compiles C applications to realize efficient custom co-processor structures for hardware acceleration on the reconfigurable logic. We show that the proposed design exploration framework can automatically generate Register Transfer Level (RTL) codes from C-functions that outperform the commercial Altera C2H RTL generator by about 40% in terms of average area-time product.

关键词： Hardware Field programmable gate arrays Optimization Registers Estimation software Multiplexing

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Native Binary Mutation Analysis for Embedded software and Virtual Prototypes in SystemC

Native Binary Mutation Analysis for Embedded Software and Vi...

引用

Pacific Rim international symposium on Dependable Computing

作者： Christoph Kuznik Wolfgang Muller Faculty of Electrical Engineering Computer Science and Mathematics C-LAB University of Paderborn Paderborn Germany

Mutation analysis is a powerful tool for white-box testing of the verification environment in order to produce dependable and higher quality software products. However, due to high computational costs and the focus on high-level software languages such as Java mutation analysis is not yet widely used in commercial design flows targeting embedded (software) systems. Here the industry is modeling both hardware and related software parts at higher levels of abstraction, called virtual prototypes, to accelerate parallel development and shorten time-to-market. In this paper we propose a mutation testing verification flow for SystemC based virtual prototypes that may not rely on source code only but on annotated basic blocks and enables mutant creation at assembler level to heavily reduce execution costs and equivalence mutants likelihood.

关键词： Prototypes Java Grammar Embedded software Embedded systems Testing

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GPU Accelerating for Rapid Multi-core Cache Simulation

GPU Accelerating for Rapid Multi-core Cache Simulation

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Wan Han Long Xiang Gao Xiaopeng Li Yi State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing China

To find the best memory system for emerging workloads, traces are obtained during application's execution, then caches with different configurations are simulated using these traces. Since program traces can be several gigabytes, simulation of cache performance is a time consuming process. Compute unified device architecture (CUDA) is a software development platform which enables programmers to accelerate the general-purpose applications on the graphics processing unit (GPU). This paper presents a real time multi-core cache simulator, which was built based on the Pin tool to get the memory reference, and fast method for multi-core cache simulation using the CUDA-enabled GPU. The proposed method is accelerated by the following techniques: execution parallelism exploration, memory latency hiding, a novel trace compression methodology. We describe how these techniques can be incorporated into CUDA code. Experimental results show that the hybrid parallel method of time-partitioning combines with set-partitioning presented here is 11.10× speedup compared to the CPU serial simulation algorithm. The present simulator can characterize cache performance of single-threaded or multi-threaded workloads at the speeds of 6-15 MIPS. It can simulates 6 cache configurations within one single pass at this speeds compared to CMP$im, which can only simulate one cache configuration each simulation pass at the speeds of 4-10 MIPS.

关键词： Graphics processing unit Instruction sets Computational modeling parallel processing Instruments Partitioning algorithms

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Exploiting Hierarchical parallelism Using UPC

Exploiting Hierarchical Parallelism Using UPC

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Lingyuan Wang Saumil Merchant Tarek El-Ghazawi Department of Electrical and Computer Engineering George Washington University USA

High-Performance Computing (HPC) systems are increasingly moving towards an architecture that is deeply hierarchical. However, the execution model with single-level parallelism embodied in legacy parallel programming models falls short in exploiting the multi-level parallelism opportunities in both hardware architectures and applications. This makes the use of richer execution models imperative in order to fully exploit hierarchical parallelism. Partitioned Global Address Space (PGAS) languages such as Unified parallel C (UPC) are growing in popularity because of their ability to provide a globally shared address space with locality awareness. While UPC provides a welcome improvement over message passing libraries, users still program with a single level of parallelism in the context of SPMD. In this paper, we explore two explicit hierarchical programming approaches based on UPC to improve programmability and performance on hierarchical architectures. The first approach orchestrates computations on multiple sets of thread groups, the second approach extends UPC with nested, shared memory multi-threading. This paper presents a detailed description of proposed approaches and demonstrates their effectiveness in the context of the NAS parallel Benchmarks and the Unbalanced Tree Search (UTS). Experimental results indicate that the hierarchical model not only provides greater expressive power but also enhances performance, all three benchmarks exceed the performance of the standard UPC implementations after being incrementally enhanced with hierarchical parallelism.

关键词： Instruction sets parallel processing Runtime Programming Three dimensional displays Electronics packaging

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