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Scalable speculative parallelization on commodity clusters 43

Scalable speculative parallelization on commodity clusters

引用

Proceedings of the 2010 43rd Annual IEEE/ACM international symposium on Microarchitecture

作者： Kim, Hanjun Raman, Arun Liu, Feng Lee, Jae W. August, David I. Departments of Electrical Engineering and Computer Science Princeton University Princeton United States Parakinetics Inc. Princeton United States

ISBN: (纸本)9780769542997

While clusters of commodity servers and switches are the most popular form of large-scale parallel computers, many programs are not easily parallelized for execution upon them. In particular, high inter-node communication cost and lack of globally shared memory appear to make clusters suitable only for server applications with abundant task-level parallelism and scientific applications with regular and independent units of work. Clever use of pipeline parallelism (DSWP), thread-level speculation (TLS), and speculative pipeline parallelism (Spec-DSWP) can mitigate the costs of inter-thread communication on shared memory multicore machines. This paper presents distributed software Multi-threaded Transactional memory (DSMTX), a runtime system which makes these techniques applicable to non-shared memory clusters, allowing them to efficiently address inter-node communication costs. Initial results suggest that DSMTX enables efficient cluster execution of a wider set of application types. For 11 sequential C programs parallelized for a 4-core 32-node (128 total core) cluster without shared memory, DSMTX achieves a geomean speedup of 49×. This compares favorably to the 15× speedup achieved by our implementation of TLS-only support for clusters. © 2010 IEEE.

关键词： Costs

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Design and implementation of parallel JiST to support distributed wireless network simulation

Design and implementation of parallel JiST to support distri...

引用

7th international symposium on High-Capacity Optical Networks and Enabling Technologies, HONET 2010

作者： Slavik, Michael Mahgoub, Imad Badi, Ahmed Ilyas, Mohammad Department of Computer Science and Engineering Florida Atlantic University Boca Raton FL United States

ISBN: (纸本)9781424499243

JiST/SWANS is a wireless network simulator gaining increasing popularity for ad-hoc wireless, wireless sensor network, and vehicular network evaluations. Typical published results using this tool show node counts on the order of hundreds of nodes. However, realistic sensor and vehicular networks may contain many more nodes than that. One reason for this discrepancy is the computational cost of evaluation via simulation. Currently, cluster computers are becoming preferred over expensive multi-processor supercomputers for improving computational output. We present the design and implementation of a parallelization of JiST, the discrete event simulator core of JiST/SWANS. JiST uses unique dynamic byte-code rewriting to simplify the development of applications and has been shown to perform well running small- or medium-scale wireless network simulations on single processor systems. We propose an optimistic cluster-based architecture and apply it to JiST. Simulation entity memory is distributed evenly across all nodes in the cluster, resulting in linear memory growth. Details of the simulation engine including the complex event execution synchronization are hidden entirely from the application, easing development and debug time. Since JiST is the simulation backend of the SWANS wireless network simulator, this result is the first step in simulating large networks using SWANS in reasonable periods of time. Results presented show the performance of our parallelization of JiST is in line with the performance of other existing parallel discrete event simulators. © 2010 IEEE.

关键词： Supercomputers

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Evaluating database-oriented replication schemes in software Transactional Memory systems

Evaluating database-oriented replication schemes in Software...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Roberto Palmieri Francesco Quaglia Paolo Romano Nuno Carvalho DIS University of Roma La Sapienza Rome Italy INESC-ID Lisboa Portugal

ISBN: (纸本)9781424465330

software Transactional Memories (STMs) are emerging as a highly attractive programming model, thanks to their ability to mask concurrency management issues to the overlying applications. In this paper we are interested in dependability of STM systems via replication. In particular we present an extensive simulation study aimed at assessing the efficiency of some recently proposed database-oriented replication schemes, when employed in the context of STM systems. Our results point out the limited efficiency and scalability of these schemes, highlighting the need for redesigning ad-hoc solutions well fitting the requirements of STM environments. Possible directions for the re-design process are also discussed and supported by some early quantitative data.

关键词： Transaction databases software systems Concurrency control Database systems Concurrent computing Memory management Application software Broadcasting Relational databases Access protocols

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Co-design of the Business and software Architectures: A systems engineering and Model-Driven Method

Co-design of the Business and Software Architectures: A Syst...

引用

ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： Xiaofeng Cui Beijing Aerospace Control Center Beijing China

ISBN: (纸本)9781424474226;9780769540887

software architecture design plays a crucial role for both the software and business success. Most of the existing methods conduct software architecture design driven by the key software requirements, facing the challenges of creating architectures from scratch and aligning with the high-level business goals. In this paper we propose the BASAD (Business And software Architecture co-Design) method to facilitate alleviating the difficulty of software architecture design and achieving the high-level business goals. The method addresses the business and software architecture design in an integrated process from a systems engineering perspective, leveraging the SysML and UML modeling languages and the automated model transformation from the business architectures to the software architectures, so that provide pragmatic support for the architecture co-design.

关键词： software architecture systems engineering and theory software design Computer architecture Design engineering software systems Unified modeling language software engineering Artificial intelligence distributed computing

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Large-scale multi-dimensional document clustering on GPU clusters

Large-scale multi-dimensional document clustering on GPU clu...

引用

24th IEEE international parallel and distributed Processing symposium, IPDPS 2010

作者： Zhang, Yongpeng Mueller, Frank Cui, Xiaohui Potok, Thomas Dept. of Computer Science North Carolina State University Raleigh NC 27695-7534 United States Oak Ridge National Laboratory Computational Sciences and Engineering Division Oak Ridge TN 37831 United States

ISBN: (纸本)9781424464432

Document clustering plays an important role in data mining systems. Recently, a flocking-based document clustering algorithm has been proposed to solve the problem through simulation resembling the flocking behavior of birds in nature. This method is superior to other clustering algorithms, including k-means, in the sense that the outcome is not sensitive to the initial state. One limitation of this approach is that the algorithmic complexity is inherently quadratic in the number of documents. As a result, execution time becomes a bottleneck with large number of documents. In this paper, we assess the benefits of exploiting the computational power of Beowulf-like clusters equipped with contemporary Graphics Processing Units (GPUs) as a means to significantly reduce the runtime of flocking-based document clustering. Our framework scales up to over one million documents processed simultaneously in a sixteen-node moderate GPU cluster. Results are also compared to a four-node cluster with higher-end GPUs. On these clusters, we observe 30X-50X speedups, which demonstrate the potential of GPU clusters to efficiently solve massive data mining problems. Such speedups combined with the scalability potential and accelerator-based parallelization are unique in the domain of document-based data mining, to the best of our knowledge. © 2010 IEEE.

关键词： Graphics processing unit

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parallel algorithms for limited views THz tomography 6

Parallel algorithms for limited views THz tomography

引用

6th World Congress in Industrial Process Tomography

作者： Ceballos, Jose Antonio Cantoral Ozanyan, Krikor B. School of Electrical and Electronic Engineering The University of Manchester ManchesterM13 9PL United Kingdom

ISBN: (纸本)9780853163220

Tomography imaging of industrial subjects requires compliance with a particular environment. This results in severe limitations on the access and the deployable hardware resources, defining the situation of imaging by systems with limited resources, to be addressed by the future generations of imagers. This means that faster and more economic implementations of data acquisition and image reconstruction are called for, enabled by the latest software and hardware developments and system *** emphasis is given to THz Tomography from limited views and the potential of the recently introduced method of sinogram restoration by sinusoidal Hough transform (HT), which has been demonstrated up-to-date only as a sequential algorithm, but is amenable to parallel computation. Possible strategies for its deployment on distributed unutilized resources in a multi-FPGA system are also discussed, including fast centre-of-mass detection, without solving the standard inverse Radon *** contribution offers a review of the approaches and methods for implementation of parallel and distributed computing for the needs of Tomography, particularly when the efficient use of dedicated resources is a priority, e.g in the case of embedded Tomography systems. We envisage generic hardware which can be configured as a multiprocessor environment, programmable to implement data acquisition, reconstruction and visualisation. The state of the art is examined and issues are highlighted from a computer science perspective, as well as from the point of view of current progress in available hardware and recent trends in reconstruction methods amenable to parallelisation. © 2014 international Society for Industrial Process Tomography.

关键词： Data acquisition

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A novel approach to automatic test case generation for Web applications

A novel approach to automatic test case generation for Web a...

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10th international Conference on Quality software, QSIC 2010

作者： Tung, Yuan-Hsin Tseng, Shian-Shyong Lee, Tsung-Ju Weng, Jui-Feng Chunghwa Telecommunication Laboratories 12 Lane 551 Min-Tsu Road Taoyuan 32617 Taiwan Department of Computer Science and Information Engineering National Chiao Tung University Taiwan Department of Information Science and Applications Asia University Taiwan

ISBN: (纸本)9780769541310

As the quantity and breadth of Web-based software systems continue to grow rapidly, it is becoming critical to assure the quality and reliability of a Web application. Web application testing is a challenging work owing to its dynamic behaviors and complex dependencies. Test case generation, in general, is costly and labor-intensive processes. How to automatically generate effective test case is important for Web applications testing. In this paper, we propose the two-phase approach to generate test cases automatically by analyzing structure of the Web application. We define the dependence relationships, data dependence and control dependence, in the Web application and detect the relationships from source code and improve the way of test case generation with analysis result. The experimental result show that our approach can reduce test case set in test case generation processes. © 2010 IEEE.

关键词： software testing

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engineering a scalable high quality graph partitioner

Engineering a scalable high quality graph partitioner

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Manuel Holtgrewe Peter Sanders Christian Schulz Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9781424464425

We describe an approach to parallel graph partitioning that scales to hundreds of processors and produces a high solution quality. For example, for many instances from Walshaw's benchmark collection we improve the best known partitioning. We use the well known framework of multi-level graph partitioning. All components are implemented by scalable parallel algorithms. Quality improvements compared to previous systems are due to better prioritization of edges to be contracted, better approximation algorithms for identifying matchings, better local search heuristics, and perhaps most notably, a parallelization of the FM local search algorithm that works more locally than previous approaches.

关键词： Partitioning algorithms Approximation algorithms parallel algorithms Clustering algorithms Application software Computer science Finite element methods Digital circuits Design methodology Process planning

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Improving the performance of hypervisor-based fault tolerance

Improving the performance of hypervisor-based fault toleranc...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Jun Zhu Wei Dong Zhefu Jiang Xiaogang Shi Zhen Xiao Xiaoming Li School of Electronics Engineering & Computer Sciences Peking University Beijing China State Key Laboratory of Advanced Optical Communication Systems & Networks Peking University Beijing China

ISBN: (纸本)9781424464425

Hypervisor-based fault tolerance (HBFT), a checkpoint-recovery mechanism, is an emerging approach to sustaining mission-critical applications. Based on virtualization technology, HBFT provides an economic and transparent solution. However, the advantages currently come at the cost of substantial overhead during failure-free, especially for memory intensive applications. This paper presents an in-depth examination of HBFT and options to improve its performance. Based on the behavior of memory accesses among checkpointing epochs, we introduce two optimizations, read fault reduction and write fault prediction, for the memory tracking mechanism. These two optimizations improve the mechanism by 31.1% and 21.4% respectively for some application. Then, we present software-superpage which efficiently maps large memory regions between virtual machines (VM). By the above optimizations, HBFT is improved by a factor of 1.4 to 2.2 and it achieves a performance which is about 60% of that of the native VM.

关键词： Fault tolerance Virtual manufacturing Virtual machine monitors Application software Fault tolerant systems Mission critical systems Read-write memory Checkpointing Virtual machining Maintenance

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Editorial: New associate editor appointments

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IEEE Transactions on Very Large Scale Integration (VLSI) systems 2010年第3期18卷 345-346页

作者： Jha, Niraj K. Department of Electrical Engineering Princeton University Princeton NJ United States

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