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An Evaluation of parallel Numerical Hessian Calculations

An Evaluation of Parallel Numerical Hessian Calculations

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23rd international symposium on High Performance Computing systems and Applications

作者： Staveley, Mark S. Poirier, Raymond A. Bungay, Sharene D. Mem Univ Newfoundland Dept Chem St John NF A1B 3X5 Canada

ISBN: (纸本)9783642126581

The calculation of the Hessian (or force constant matrix), is an important part of geometry optimization calculations. The process of calculating the Hessian can be demanding in both computational time and resources. Even though many computational chemistry software packages make use of numerical Hessian calculations, very little has been published with respect to the performance and accuracy traits of this type of calculation. This paper presents the following: a comparison of different parallelization methods as they are applied to the numerical Hessian calculation;the accuracy of the results produced by these different parallelization methods;and an evaluation that compares the performance of the numerical Hessian parallel algorithm on different system configurations.

关键词： Computational Chemistry parallelization Numerical Hessian Geometry Optimization Calculations

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Towards sustainability in portable computing through cloud computing and cognitive radios

Towards sustainability in portable computing through cloud c...

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international Workshop on Scheduling and Resource Management for parallel and distributed systems

作者： Namboodiri, Vinod Department of Electrical Engineering and Computer Science Wichita State University Wichita KS United States

ISBN: (纸本)9780769541570

It is imperative to consider the concept of sustainable portable computing as the role of such devices increases our lives. With the emergence of the cloud computing paradigm, there will be an increased reliance on wireless communication from portable computing devices to more powerful centralized servers. This paradigm shift to 'thin-clients' presents an opportunity to make portable computing more sustainable by shifting more functionality to centralized servers. Reduced functionality needed on these devices could mean a slower rate of hardware replacement. This could significantly cut the electronic waste that is currently attributed to the frequent replacements of these devices. One of the challenges in such a paradigm shift to thin portable clients through reduced local computation would be the additional burden imposed on the wireless communication technologies used. Wireless communication technologies must be improved to handle the additional burden that will be imposed. Any proposed wireless technology must also be energyefficient to maximize the operating life time of these battery operated, energy-constrained devices. software approaches to achieve energy-efficient operation are preferable as they reduce the dumping of existing hardware due to upgrades or replacements, and help reduce electronic waste. This paper discusses these challenges and describes one way to move forward towards sustainable portable computing by considering application scenarios based on cloud computing and communication through software-defined cognitive radios. © 2010 IEEE.

关键词： Electronic Waste

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A Methodology for the Use of the Teleo-Reactive Programming Technique in Autonomic Computing

A Methodology for the Use of the Teleo-Reactive Programming ...

引用

ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： James Hawthorne Richard Anthony James Hawthorne Richard Anthony University of Greenwich London UK

ISBN: (纸本)9781424474226;9780769540887

Previous work on the use of the Teleo-Reactive technique in high level software development has shown it to be a viable approach for autonomic systems. A T-R program can recover from unexpected events without knowing the underlying source or cause of the problem and thus reduces the maintenance costs of software projects where unexpected events are a likely and frequent occurrence. Previous work has also highlighted the difficult nature of designing and structuring the high level logic in a T-R program and so this work aims to reduce the problem by providing a software engineering strategy that will both drive the program development and reduce the occurrence of logic problems.

关键词： software maintenance distributed computing software engineering Artificial intelligence Computer networks Concurrent computing Logic design Robot sensing systems Mathematical programming parallel programming

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Algorithm engineering for scalable parallel external sorting

Algorithm engineering for scalable parallel external sorting

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Peter Sanders Karlsruher Institut für Technologie Karlsruhe Germany

The talk describes algorithm engineering (AE) as a methodology for algorithmic research where design, analysis, implementation and experimental evaluation of algorithms form a feedback cycle driving the development of efficient algorithm. Additional important components of the methodology include realistic models, algorithm libraries, and collections of realistic benchmark instances. We use one main example throughout this paper: sorting huge data sets using many multi-core processors and disks. The described system is the current record holder for the GraySort and MinuteSort sorting benchmarks.

关键词： Sorting Algorithm design and analysis Application software Design engineering Libraries Data engineering Reliability engineering Feedback Multicore processing Data structures

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Runtime checking of serializability in software transactional memory

Runtime checking of serializability in software transactiona...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Arnab Sinha Sharad Malik Department of Electrical Engineering Princeton University USA

Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these are limited in the scale of systems they can handle and generally verify only a model of the system, and not the actual system. In this paper we present an alternate attack on checking the correctness of an STM implementation by verifying the execution runs of an STM using a checker that runs in parallel with the transaction memory system. With future many-core systems predicted to have hundreds and even thousands of cores, it is reasonable to utilize some of these cores for ensuring the correctness of the rest of the system. This will be needed anyway given the increasing likelihood of dynamic errors due to particle hits (soft errors) and increasing fragility of nanoscale devices. These errors can only be detected at runtime. An important correctness criterion that is the subject of verification is the serializability of transactions. While checking transaction serializability is NP-complete, practically useful subclasses such as interchange-serializability (DSR) are efficiently computable. Checking DSR reduces to checking for cycles in a transaction ordering graph which captures the access order of objects shared between transaction instances. Doing this concurrent to the main transaction execution requires minimizing the overhead of capturing object accesses, and managing the size of the graph, which can be as large as the total number of dynamic transactions and object accesses. We discuss techniques for minimizing the overhead of access logging which includes time-stamping, and present techniques for on-the-fly graph compaction that drastically reduce the size of the graph that needs to be maintained, to be no larger than the number of threads. We have implemented concurrent serializability checking in the Rochester software Transactional Memory (RSTM) system. We present our practical experienc

关键词： Runtime State-space methods Debugging Formal verification Nanoscale devices Explosions Application software software systems Compaction

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Automatic Query Generation in Guided systems: Natural Language Generation from Graphically Built Query

Automatic Query Generation in Guided Systems: Natural Langua...

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ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： Sara Paiva Manuel Ramos-Cabrer Alberto Gil-Solla Viana do Castelo Polytechnic Institute Viana do Castelo Portugal Vigo University Vigo Spain

ISBN: (纸本)9781424474226;9780769540887

Guided-based systems are an alternative to natural language systems regarding the query construction method. We present a new solution that bridges the gap between these two types of systems by providing a hybrid interface which combines a graphical query interface for query construction with the correspondent natural language expression automatically generated by the system.

关键词： Natural languages Buildings Hybrid power systems Ontologies software engineering Artificial intelligence distributed computing Bridges Search engines Usability

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Intelligent Framework for the Management of distributed Architectures

Intelligent Framework for the Management of Distributed Arch...

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ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： D. Ong S. Khaddaj Faculty of Computing Information Systems and Mathematics Kingston London University Kingston upon Thames UK

ISBN: (纸本)9781424474226;9780769540887

The continuous decentralisation and distribution of software, hardware, and human resources depends on a number of fundamental factors including the ability to provide desired Quality of Service (QoS) on resources assembled dynamically from enterprises, service providers and customer systems. Despite recent developments there are still many challenges in efficient information delivery and management services for distributed architectures. In this work we are particularly interested with the use of intelligent decision making mechanisms for the management of distributed architectures. Our research aims at designing and developing an intelligent decision making mechanism for the management, distribution, control and optimisation of systems resources within large distributed systems which allows dynamic system architecture configuration and provisioning.

关键词： Computer architecture Quality of service Decision making software quality Hardware Humans Assembly systems Information management Resource management Control systems

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Scalable multi-pipeline architecture for high performance multi-pattern string matching

Scalable multi-pipeline architecture for high performance mu...

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24th IEEE international parallel and distributed Processing symposium, IPDPS 2010

作者： Jiang, Weirong Yang, Yi-Hua E. Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA 90089 United States

ISBN: (纸本)9781424464432

Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho-Corasick deterministic finite automaton (AC-DFA) based solutions produce deterministic throughput and are widely used in today's DPI systems such as Snort [1] and ClamAV [2], the high memory requirement of AC-DFA (due to the large number of state transitions in AC-DFA) inhibits efficient hardware implementation to achieve high performance. Some recent work [3], [4] has shown that the AC-DFA can be reduced to a character trie that contains only the forward transitions by incorporating pipelined processing. But they have limitations in either handling long patterns or extensions to support multi-character input per clock cycle to achieve high throughput. This paper generalizes the problem and proves formally that a linear pipeline with H stages can remove all cross transitions to the top H levels of a AC-DFA. A novel and scalable pipeline architecture for memory-efficient multi-pattern string matching is then presented. The architecture can be easily extended to support multi-character input per clock cycle by mapping a compressed AC-DFA [5] onto multiple pipelines. Simulation using Snort and ClamAV pattern sets shows that a 8-stage pipeline can remove more than 99% of the transitions in the original AC-DFA. The implementation on a state-of-the-art field programmable gate array (FPGA) shows that our architecture can store on a single FPGA device the full set of string patterns from the latest Snort rule set. Our FPGA implementation sustains 10+ Gbps throughput, while consuming a small amount of on-chip logic resources. Also desirable scalability is achieved: the increase in resource requirement of our solution is sub-linear with the throughput improvement. © 2010 IEEE.

关键词： Pipelines

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Building multi-kernel embedded system on PAC multi-core platform

Building multi-kernel embedded system on PAC multi-core plat...

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10th international Conference on Quality software, QSIC 2010

作者： Chen, Jing Young, Chung-Ping Chang, Da-Wei Huang, Guan-Ying Ke, Chung-Yuan Yen, Shih-Tun Kuo, Tsang-Shuo Department of Electrical Engineering National Cheng Kung University No. 1 University Road Tainan City Taiwan Department of Computer Science and Information Engineering National Cheng Kung University No. 1 University Road Tainan City Taiwan

ISBN: (纸本)9780769541310

It is common nowadays that consumer embedded system products are built on platforms with System-On-a-Chip (SOC) in which two or more processor cores, which are not necessarily of the same type, are put into a single chip and form the architecture of Chip-level Multi-Processor (CMP). Although such platform is capable of achieving high performance at relatively low cost, the system architecture of CMP brings new design challenges as well as increased complexity in developing embedded software especially at the level of kernel or operating system software. This paper presents our experience and some preliminary results from the project of building a multi-kernel embedded system platform for application software running in the environment of a newly developed multi-core SOC, namely PAC Duo SOC, which is the latest product from the PAC (short for parallel Architecture Core) Project initiated by the Industry Technology Research Institute (ITRI) in Taiwan. PAC Duo SOC is a chip-level heterogeneous multi-processor SOC composed of one ARM926 core serving as the general purpose processor (GPP for short) and two ITRI PAC DSP cores serving as the special purpose processors (SPP). We ported Linux operating system to run on the ARM926 processor and ported μC/OS-II real-time kernel to run on one PAC DSP core, leaving the other PAC DSP core with the option, for flexibility, of running either μC/OS-II or a different kernel. In addition, an inter-processor communication (IPC) mechanism is developed which not only takes application-specific requirements into account but also takes advantages of hardware features. © 2010 IEEE.

关键词： Embedded systems

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User and Item Pattern Matching in Multi-criteria Recommender systems

User and Item Pattern Matching in Multi-criteria Recommender...

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ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： Pitaya Poompuang Wichian Premchaiswadi Graduate School of IT in Business Siam University Bangkok Thailand

ISBN: (纸本)9781424474226;9780769540887

Information on the ratings of several features of items can be deployed to improve the quality of recommendations in recommender systems by incorporating them into similarity calculation between any two users or two items. However, the incremental information of these features has important impacts on recommender systems. For example, the complexity of similarity calculation is increased and more resources are consumed during the process for generating recommendations. In this paper, we propose several techniques by using this information to provide relevant recommendations and to reduce the complexity in similarity computation by directly matching between preferences of user and the strength of item features.

关键词： Pattern matching Recommender systems Motion pictures Multidimensional systems Information filtering Information filters software engineering Artificial intelligence distributed computing software standards

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