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检索条件"任意字段=International Symposium on Software Engineering for Parallel and Distributed Systems"

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Proficiency Metrics for Failure Prediction in High Performance Computing

Proficiency Metrics for Failure Prediction in High Performan...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Narate Taerat Chokchai Leangsuksun Clayton Chandler Nichamon Naksinehaboon College of Engineering & Science Louisiana Tech University Ruston LA USA

The number of failures occurring in large-scale high performance computing (HPC) systems is significantly increasing due to the large number of physical components found on the system. Fault tolerance (FT) mechanisms help parallel applications mitigate the impact of failures. However, using such mechanisms requires additional overhead. As such, failure prediction is needed in order to smartly utilize FT mechanisms. Hence, the proficiency of a failure prediction determines the efficiency of FT mechanism utilization. The proficiency of a failure predictor in HPC is usually designated by well-known error measurements, e.g. MSE, MAD, precision and recall, in which less error infers the greater proficiency. In this manuscript, we propose to view prediction proficiency from another aspect-lost computing time. We then discuss the insufficiency of error measurements as HPC failure prediction proficiency metrics from the aspect of lost computing time, and propose novel metrics that address these issues.

关键词： Measurement uncertainty Predictive models Loss measurement Time measurement Computational modeling Time series analysis

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AUTO-GC: Automatic translation of data mining applications to GPU clusters

AUTO-GC: Automatic translation of data mining applications t...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Wenjing Ma Gagan Agrawal Department of Computer Science and Engineering Ohio State Uinversity Columbus OH USA

ISBN: (纸本)9781424465330

Because of the very favorable price to performance ratio of the GPUs, a popular parallel programming configuration today is a cluster of GPUs. However, extracting performance on such a configuration would typically require programming in both MPI and CUDA, thus requiring a high degree of expertise and effort. It is clearly desirable to be able to support higher-level programming of this emerging high-performance computing platform. This paper reports on a code generation system that can translate data mining applications on a GPU cluster. Our work is driven by the observation that a common processing structure, that of generalized reductions, fits a large number of popular data mining algorithms. In our solution, the programmers simply need to specify the sequential reduction loop(s) with some additional information about the parameters. We use program analysis and code generation to automatically map the applications to the API of FREERIDE, which is a middleware for parallel data mining. We also automatically generate CUDA code for using the GPU on each node of the cluster. We have evaluated our system using two popular data mining applications, k-means clustering and Principal Component Analysis (PCA). We observed good scalability over the number of computing nodes, and the automatically generated version did not have any noticeable overheads compared to hand written codes. The speedup obtained by using GPU over using only the CPU on each node of a cluster is between 3 and 21.

关键词： Data mining Middleware Principal component analysis parallel programming Programming profession Scalability parallel processing Application software Computer science Data engineering

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Weak execution ordering - exploiting iterative methods on many-core GPUs

Weak execution ordering - exploiting iterative methods on ma...

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IEEE international symposium on Performance Analysis of systems and software

作者： Jianmin Chen Zhuo Huang Feiqi Su Jih-Kwon Peir Jeff Ho Lu Peng Department of Computer and Information Science and Engineering University of Florida Gainesville FL USA Department of Electrical and Computer Engineering Louisiana State University Baton Rouge LA USA

ISBN: (纸本)9781424460236;9781424460229

On NVIDIA's many-core GPUs, there is no synchronization function among parallel thread blocks. When fine-granularity of data communication and synchronization is required for large-scale parallel programs executed by multiple thread blocks, frequent host synchronization are necessary, and they incur a significant overhead. In this paper, we investigate a class of applications which uses a chaotic version of iterative methods [5], [22] to obtain numerical solutions for partial differential equations (PDE). Such a fast PDE solver is parallelized on GPUs with multiple thread blocks. In this parallel implementation, although frequent data communication is needed between adjacent thread blocks, a precise order of the data communication is not necessary. Separate communication threads are used for periodically exchanging the boundary values with adjacent thread blocks through the global memory. Since a precise order of the data communication is not required, the computation and the communication threads can be overlapped to alleviate the communication overhead. Performance measurements of two popular applications, Poisson image editing from computer graphics and shape from shading from computer vision, on Tesla C1060 show that a speedup of 4-5 times is achievable for both applications in comparison with the solution using host synchronization.

关键词： Iterative methods Multicore processing Data communication Application software Large-scale systems Chaotic communication Partial differential equations Graphics processing unit Shape measurement Computer vision

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Support of cross calls between a microprocessor and FPGA in CPU-FPGA coupling architecture

Support of cross calls between a microprocessor and FPGA in ...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Giang Nguyen thi Huong Seon Wook Kim School of Electrical Engineering Korea University Seoul South Korea

ISBN: (纸本)9781424465330

The coupling architecture containing an FPGA device and a microprocessor has been widely used to accelerate microprocessor execution. Therefore, there have been intensive researches about synthesizing high-level programming languages (HLL) such as C and C++ into HW in the high-level synthesis community in order to make the work of reconfiguring the FPGA easier. However, the difference in a calling method in terms of semantics between HDLs and HLLs makes their interface implementation very difficult. This paper presents a novel communication framework between a microprocessor and FPGA, which allows the full implementation of cross calls between SW and HW and even recursive calls in HW without any limitation. We show that our proposed calling overhead is very small. With our communication framework, hardware components inside the FPGA are no longer isolated accelerators, and they can work as other master components in a system configuration.

关键词： Microprocessors Field programmable gate arrays Hardware design languages software performance Computer languages Ash Acceleration High level synthesis Digital signal processing Programming

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Bagging of Complementary Neural Networks with Double Dynamic Weight Averaging

Bagging of Complementary Neural Networks with Double Dynamic...

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ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： Sathit Nakkrasae Pawalai Kraipeerapun Somkid Amornsamankul Chun Che Fung Department of Computer Science Faculty of Science Ramkhamhaeng University Bangkok Thailand Department of Mathematics Faculty of Science Thailand and Centre of Excellence in Mathematics CHE Mahidol University Bangkok Bangkok Thailand School of Information Technology Murdoch University Perth Australia

ISBN: (纸本)9781424474226;9780769540887

Ensemble technique has been widely applied in regression problems. This paper proposes a novel approach of the ensemble of Complementary Neural Network (CMTNN) using double dynamic weight averaging. In order to enhance the diversity in the ensemble, different training datasets created based on bagging technique are applied to an ensemble of pairs of feed-forward back-propagation neural networks created to predict the level of truth and falsity values. In order to obtain more accuracy, uncertainties in the prediction of truth and falsity values are used to weight the prediction results in two steps. In the first step, the weight is used to average the truth and the falsity values whereas the weight in the second step is used to calculate the final regression output. The proposed approach has been tested with benchmarking UCI data sets. The results derived from our technique improve the prediction performance while compared to the traditional ensemble of neural networks which is predicted based on only the truth values. Furthermore, the obtained results from our novel approach outperform the results from the existing ensemble of complementary neural network.

关键词： Bagging Neural networks Natural languages Buildings Hybrid power systems Ontologies software engineering Artificial intelligence distributed computing Bridges

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Enhanced Privilege Separation for Commodity software on Virtualized Platform

Enhanced Privilege Separation for Commodity Software on Virt...

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international Conference on parallel and distributed systems (ICPADS)

作者： Mingyuan Xia Miao Yu Qian Lin Zhengwei Qi Haibing Guan School of Electronic Information and Electrical Engineering School of Software Engineering Shanghai Jiaotong University Shanghai China

Conventional privilege separation can effectively reduce the TCB size by granting privilege to only the privileged compartments. However, since they this approach relies on process isolation to ensure security assurance, malware exploiting against kernel components can easily compromise. Meanwhile, the frequent inter-process communications between separated processes inevitably incur notable overhead. To ameliorate these problems, we propose to perform privilege separation without partitioning application into two processes. Instead, we leverage virtualization to enforce the isolation of sensitive portions from other untrusted code. The virtual machine monitor intercepts all the code context switches transparently without requiring the application to explicitly use IPC as privilege context transition. We have implemented a prototype of our system, named Coir, based on commodity hypervisor Xen. Evaluation of our prototype includes a real-world remote control application, which is partitioned and protected in Coir-enabled hypervisor on unmodified Windows XP. We discuss the isolation strength as well as the performance penalty of our system based on the practical case.

关键词： Security Virtual machine monitors Runtime Prototypes Context Kernel Monitoring

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High-reliability and harmonic-sharing dual parallel topology for active power filter

High-reliability and harmonic-sharing dual parallel topology...

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IEEE international symposium on Power Electronics for distributed Generation systems (PEDG)

作者： Jianjun Sun Baifeng Chen Suxuan Guo Xiaoming Zha Lan Xiong Jinwu Gong School of Electrical Engineering Wuhan University of China Wuhan China

This paper chooses the proportional resonant controller for the controlling of Active Power Filter, and proposed a new control topology for dual parallel APF application. The APF_I near the load side employs the proportional resonant controller to compensate the 5 th , 11 th , 17 th and 23 rd harmonics; The APF_II near the system side also employs the proportional resonant controller to compensate the 7 th , 13 th , 19 th and 25 th harmonics. Both APF_I and APF_II choose the system side harmonic current for feedback control, and also have fast dynamic response due to the proportional resonant controllers. Compared with traditional dual parallel APF, this topology let two parallel APFs have different compensation characteristic, which could compensate selected harmonics and realize harmonic sharing. When one of them is out of working, the other APF could still compensate almost half of all harmonics. Proposed parallel system has advantage for system expansion, cost saving and power-rate improving. The circuit currents for different harmonics are also discussed. This paper analysis the system characteristic and design the system configuration and control parameters. The simulation on MATLAB/simulink also demonstrates the validity and superiority of proposed system configuration and control strategy.

关键词： Harmonic analysis Power harmonic filters Control systems Active filters Topology Frequency control

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Acceleration of a High Order Accurate Method for Compressible Flows on SDSM Based GPU Clusters

Acceleration of a High Order Accurate Method for Compressibl...

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international Conference on parallel and distributed systems (ICPADS)

作者： Konstantinos I. Karantasis Eleftherios D. Polychronopoulos John A. Ekaterinaris High Performance Information Systems Laboratory School of Computer Engineering and Informatics University of Patras Rio Greece School of Mechanical and Aerospace Engineering University of Patras Rio Greece

The recent advent of multicore processors, and especially the introduction of many-core GPUs, opens new horizons to large-scale, high-resolution, simulations for a broad range of scientific fields. Among them, the scientific area of CFD appears to be one of the candidates that could significantly benefit from the utilization of many-core GPUs. In o rder to investigate such a potential, we evaluate the performance of a high-order accurate method for the simulation of compressible flows. Current implementation is taking place on a GPU cluster. Nevertheless, a novel approach is followed concerning the utilization of GPU clusters that does not involve explicit message passing. Instead, the presented implementation resides on software distributed Shared Memory (SDSM) to propagate changes across the simulation phases. The first results prove to be emboldening and lay grounds for further research along the use of shared memory abstraction in order to utilize future GPU clusters.

关键词： Graphics processing unit Computational modeling Three dimensional displays Instruction sets Numerical models Solid modeling Multicore processing

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Reconfigurable architecture for mathematical morphology using genetic programming and FPGAs

Reconfigurable architecture for mathematical morphology usin...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Emerson Carlos Pedrino Osmar Ogashawara Valentin Obac Roda Department of Computer Science Federal University of São Carlos Sao Paulo Brazil Department of Electrical Engineering University of São Paulo Sao Paulo Brazil

ISBN: (纸本)9781424465330

The task of designing manually morphological operators for a given application is not always a trivial one. Genetic programming is a branch of evolutionary computing and it is consolidating as a promising method for applications of digital image processing. The main objective of genetic programming is to discover how computers can learn to solve problems without being programmed for that. In the literature little has been found about the automatic morphological construction of operators using genetic programming. In this paper, it's presented an original architecture implemented in a FPGA for classical mathematical morphological (binary and gray level) operations that are generated automatically by a genetic programming approach. The possible applications for the system are: pattern recognition and emulation of simple filters, to name just a few. Practical examples using the developed system are presented.

关键词： Reconfigurable architectures Morphology Genetic programming Field programmable gate arrays Application software Digital images Computer architecture Pattern recognition Emulation Filters

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FTCloud: A Component Ranking Framework for Fault-Tolerant Cloud Applications

FTCloud: A Component Ranking Framework for Fault-Tolerant Cl...

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international symposium on software Reliability engineering (ISSRE)

作者： Zibin Zheng Tom Chao Zhou Michael R. Lyu Irwin King Department of Computer Science and Engineering Chinese University of Hong Kong New Territories Hong Kong China

Cloud computing is becoming a mainstream aspect of information technology. The cloud applications are usually large-scale, complex, and include a lot of distributed components. Providing highly reliable cloud applications is a challenging and critical research problem. To attack this challenge, we propose FTCloud which is a component ranking based framework for building fault-tolerant cloud applications. FTCloud employs the component invocation structures and the invocation frequencies to identify the significant components in a cloud application. An algorithm is proposed to automatically determine optimal fault tolerance strategy for these significant components. The experimental results show that by tolerating faults of a small part of the most significant components, the reliability of cloud application can be greatly improved.

关键词： Clouds Fault tolerance Fault tolerant systems Algorithm design and analysis software reliability software

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