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Head-body partitioned string matching for Deep Packet Inspection with scalable and attack-resilient performance

Head-body partitioned string matching for Deep Packet Inspec...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Yi-Hua E. Yang Viktor K. Prasanna Chenqian Jiang Ming Hsieh Department of Electrical Engineering University of Southern California USA

Dictionary-based string matching (DBSM) is a critical component of Deep Packet Inspection (DPI), where thousands of malicious patterns are matched against high-bandwidth network traffic. Deterministic finite automata constructed with the Aho-Corasick algorithm (AC-DFA) have been widely used for solving this problem. However, the state transition table (STT) of a large-scale DBSM AC-DFA can span hundreds of megabytes of system memory, whose limited bandwidth and long latency could become the performance bottleneck We propose a novel partitioning algorithm which converts an AC-DFA into a ¿head¿ and a ¿body¿ parts. The head part behaves as a traditional AC-DFA that matches the pattern prefixes up to a predefined length; the body part extends any head match to the full pattern length in parallel body-tree traversals. Taking advantage of the SIMD instructions in modern x86-64 multi-core processors, we design compact and efficient data structures packing multi-path and multi-stride pattern segments in the body-tree. Compared with an optimized AC-DFA solution, our head-body matching (HBM) implementation achieves 1.2x to 3x throughput performance when the input match (attack) ratio varies from 2% to 32%, respectively. Our HBM data structure is over 20x smaller than a fully-populated AC-DFA for both Snort and ClamAV dictionaries. The aggregated throughput of our HBM approach scales almost 7x with 8 threads to over 10 Gbps in a dual-socket quad-core Opteron (Shanghai) server.

关键词： Inspection Pattern matching Partitioning algorithms Data structures Throughput Telecommunication traffic Automata Large-scale systems Bandwidth Delay

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Scalable multi-pipeline architecture for high performance multi-pattern string matching

Scalable multi-pipeline architecture for high performance mu...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Weirong Jiang Yi-Hua E. Yang Viktor K. Prasanna Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA USA

Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho-Corasick deterministic finite automaton (AC-DFA) based solutions produce deterministic throughput and are widely used in today's DPI systems such as Snort [1] and ClamAV [2], the high memory requirement of AC-DFA (due to the large number of state transitions in AC-DFA) inhibits efficient hardware implementation to achieve high performance. Some recent work [3], [4] has shown that the AC-DFA can be reduced to a character trie that contains only the forward transitions by incorporating pipelined processing. But they have limitations in either handling long patterns or extensions to support multi-character input per clock cycle to achieve high throughput. This paper generalizes the problem and proves formally that a linear pipeline with H stages can remove all cross transitions to the top H levels of a AC-DFA. A novel and scalable pipeline architecture for memory-efficient multi-pattern string matching is then presented. The architecture can be easily extended to support multi-character input per clock cycle by mapping a compressed AC-DFA [5] onto multiple pipelines. Simulation using Snort and ClamAV pattern sets shows that a 8-stage pipeline can remove more than 99% of the transitions in the original AC-DFA. The implementation on a state-of-the-art field programmable gate array (FPGA) shows that our architecture can store on a single FPGA device the full set of string patterns from the latest Snort rule set. Our FPGA implementation sustains 10+ Gbps throughput, while consuming a small amount of on-chip logic resources. Also desirable scalability is achieved: the increase in resource requirement of our solution is sub-linear with the throughput improvement.

关键词： Throughput Pipelines Field programmable gate arrays Clocks Intrusion detection Inspection Automata Hardware Memory architecture Programmable logic arrays

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VMeter: Power modelling for virtualized clouds

VMeter: Power modelling for virtualized clouds

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Ata E Husain Bohra Vipin Chaudhary Department of Computer Science and Engineering State University of New York NY USA

ISBN: (纸本)9781424465330

Data centers are seeing unprecedented growth in recent years. The energy requirements to operate these large scale facilities are increasing significantly both in terms of operation cost as well as their indirect impact on ecology due to high carbon emissions. There are several ongoing research efforts towards the development of an integrated cloud management system to provide comprehensive online monitoring of resource utilization along with the implementation of power-aware policies to reduce the total energy consumption. However, most of these techniques provide online power monitoring based on the power consumption of a physical node running one or more Virtual Machines (VM). They lack a fine-grained mechanism to profile the power of an individual hosted VM. In this work we present a novel power modelling technique, VMeter, based on online monitoring of system-resources having high correlation with the total power consumption. The monitored system sub-components include: CPU, cache, disk, and DRAM. The proposed model predicts instantaneous power consumption of an individual VM hosted on a physical node besides the full system power consumption. Our model is validated using computationally diverse and industry standard benchmark programs. Our evaluation results show that our model is able to predict instantaneous power with an average mean and median accuracy of 93% and 94%, respectively, against the actual measured power using an externally attached power meter.

关键词： Clouds Energy consumption Power system modeling Virtual manufacturing Resource management Virtual machine monitors Predictive models Biological system modeling Large-scale systems Costs

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Seamless On-Line Service Upgrade for Transaction-Based Internet Services

Seamless On-Line Service Upgrade for Transaction-Based Inter...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Hung-Siang Chang Yu-Sheng Liao Yi-Hsiang Huang Chung-Keng Hung Chi-Sheng Shih Phone Lin Embedded Systems and Wireless Networking Laboratory Graduate Institute of Networking and Multimedia Department of Computer Science and Information Engineering National Taiwan University Taiwan

Internet services are now the major service platforms to provide services for all sectors of business and industries. To assure the correctness for concurrent data access, transaction-based Internet service is a well-accepted computation model. Because of the proliferation of networked devices and globalization, internet services can barely undertake any service interruption during any time of the day. Service interruption includes scheduled service upgrade, bug fixes, power outage, and service attacks. While considering the QoS (Quality of Service) for the transaction-based Internet service, service continuity is not negligible. However, transaction-base service model does not guarantee service continuity and could lessen the quality of service in many circum-stances. Although several service continuity technologies are developed, many of them focus on providing backup service when failure occurs and do not guarantee that the clients can continue their requested services step when the system is back to service. Existing technologies that support on-line service upgrade are usually too complicated to implement or have tremendous runtime overhead. In this paper, we describe the design, implementation and performance evaluation for service continuity technology to provide seamless online service upgrade for transaction-based Internet services. This approach requires minimal amount of code rewriting and has least overhead, comparing with existing approaches. We present the performance evaluation results and show that the overhead of our design is negligible.

关键词： Web server Web and internet services Prototypes Java Transmission line measurements Databases

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Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures

Exploiting FPGAs for technology-aware system-level evaluatio...

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IEEE international symposium on Performance Analysis of systems and software

作者： Simone Secchi Paolo Meloni Luigi Raffo DIEE-Department of Electrical and Electronic Engineering University of Cagliari Cagliari Italy

ISBN: (纸本)9781424460236;9781424460229

The hardware-software co-development of modern complex MPSoC computing platforms exposes to the designer a huge complexity, resulting from the combination of vastly different architectural possibilities with strict demands posed by the target applications. To handle this complexity, highly accurate but rapid prototyping/evaluation environments need to be developed, that would possibly be able to provide an effective measurement of the system under design as soon as possible, allowing to comply with current time-to-market. While software-based fully cycle-accurate simulators do not seem to represent anymore an adequate solution to solve this issue, the attention has been recently shifted to the adoption of hardware emulators in the early stages of the design flow. In this work, we present an emulation framework for library-based semiautomatic instantiation of complex multi-core platforms that exploits FPGA devices to provide detailed functional information on the platform under development, and at the same time using hardware execution traces with technology-related analytical models to extract, already at system-level, physical metrics on power consumption, maximum operating frequency and area occupation of a prospective ASIC implementation of the system. Two prospective use case scenarios are presented to validate the usefulness of the presented framework: the first one analyzes the mapping and the scalability of a highly parallel application over a 2D homogeneous mesh architecture for increasing number of processors, while the second one employs the emulation infrastructure inside a design space exploration flow for the configuration of some interconnection network parameters.

关键词： Field programmable gate arrays Hardware Emulation Computer architecture Application software software prototyping Prototypes Current measurement Time to market Analytical models

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Optimal task scheduler for multi-core processor

Optimal task scheduler for multi-core processor

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international Conference on software Technology and engineering (ICSTE)

作者： Vinay G. Vaidya Sudhakar Sah Priti Ranadive Center of Research in Engineering Sciences and Technology KPIT Cummins Infosystems Limited Pune Maharashtra India

With the advent of multi-core processors, parallel execution of multiple tasks has become a common practice. Various scheduling algorithms have addressed this issue considering multiprocessor systems. Most of these algorithms target application level parallelism. Task level parallelism within an application can be exploited using shared memory architecture such as multi-core processor or in a distributed computing environment. In this paper, we propose a static scheduling algorithm that generates a schedule that can be optimized for one or all parameters including execution time, number of processors, and efficiency of processors. The input to this scheduler is a task dependency matrix is generated using dependency analysis technique. Efficiency of this scheduler is high because it uses multiple parameters such as task wait time, number of tasks whose dependency gets resolved by scheduling a task, and task execution time. The paper concludes with an example of applying this technique to a set of tasks.

关键词： Program processors Hardware Fires

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The Code Obfuscation Technology Based on Class Combination

The Code Obfuscation Technology Based on Class Combination

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The Ninth international symposium on distributed Computing and Applications to Business,engineering and Science

作者： XIANG Guangli School of Computer Science and Technology Wuhan University of Technology Wuhan,China CAI Zheng School of Computer Science and Technology Wuhan University of Technology Wuhan,China

Along with the development of the Internet and distributed systems,it requires that the software is irrelative with the runtime platform,and can be *** how to protect mobile code from malicious host is a new issue that cannot be dealt by traditional *** this condition,the Java *** the JVM instruction system is too simple,but its class format includes a lot of information which is useful for the anti-compiling. The obfuscation can prevent the java program from reverse-engineering effectively,and source codes which de-compiler got cannot read *** paper discusses the method of the combined class of code obfuscation;and simultaneously the definition, classification and standard judgment of the Obfuscation technology are given.

关键词： software Protection Combined Class Code Obfuscation.

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Optimization and Implementation of LBM Benchmark on Multithreaded GPU

Optimization and Implementation of LBM Benchmark on Multithr...

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international Conference on Data Storage and Data engineering (DSDE)

作者： Xiaoguang Ren Yuhua Tang Guibin Wang Tao Tang Xudong Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781424456789;9780769539584

With fast development of transistor technology, Graphic Processing Unit(GPU) is increasingly used in the non-graphics applications, and major GPU hardware vendors have introduced software stacks for their own GPUs, such as Brook+ for AMD GPU. Compared with the traditional parallel systems, heterogeneous systems integerating stream-based multi-threaded GPUs provide higher parallel computing capabilities with lower cost. However, porting traditional applications to the heterogeneous systems makes new demand of application optimization on GPU. Based on the AMD's Brook+ platform, we explored application optimization features on AMD GPU by optimizing and implementing the benchmark LBM from SPEC2006. To improve the program locality, we optimized the original data layout of LBM. Using the short vector data types mechanism provided by Brook+, we also optimized the GPU's bandwidth utilization and its thread processors' efficiency. Through the branch elimination technique, we reduced the performance lose caused by branch divergences in the kernel, which is due to the GPU's SIMD executing mode. The experiment results show that data layout, memory bandwidth, branch paths and other factors have a close effect on the performance of program execution on the GPU. Through all the optimizations, we finally got a speedup of 22x (single-precision) and 19x (double-precision) over the original serial benchmark code on a Quad-core CPU, and a speedup of 4x (single-precision) and 8.7x (double-precision) over the original OMP benchmark code on a 8-core CPU.

关键词： Application software Graphics processing unit parallel processing Computer architecture Biomedical computing Computational fluid dynamics Computational modeling

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Approximate Data Collection for Wireless Sensor Networks

Approximate Data Collection for Wireless Sensor Networks

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international Conference on parallel and distributed systems (ICPADS)

作者： Chao Wang Huadong Ma Yuan He Shuguang Xiong Beijing Key Laboratory of Intelligent Telecommunication Software and Multimedia Beijing University of Posts and Telecommunications Beijing China Department of Computer Science and Engineering Hong Kong University of Science and Technology Hong Kong China Department of Computer Science and Technology Harbin Institute of Technology Harbin China

Data collection is a fundamental issue in wireless sensor networks. In many application scenarios for sensor networks, approximate data collection is a wise choice due to the constraints in communication bandwidth and energy budget. In this paper, we focus on efficient approximate data collection with given error bounds in wireless sensor networks. The key idea of our data collection approach ADC (Approximate Data Collection) is to divide a sensor network into clusters, discover local data correlations on each cluster head, and perform a global approximate data collection on the sink according to model parameters uploaded by cluster heads. Specifically, we propose a local estimation model to approximate the readings of several subsets of sensor nodes, and prove rated error-bounds of data collection using this model. In the process of model-based data collection, we formulate the problem of selecting the minimum subset of sensor nodes into a minimum dominating set problem which is known to be NP-hard, and use a greedy heuristic algorithm to find an approximate solution. We also propose a monitoring algorithm to adjust these subsets according to the changes of sensor readings. Our trace-driving simulation results show that our data collection approach ADC can notably reduce the communication cost with given error bounds.

关键词： Approximation methods Estimation Data models Correlation Approximation algorithms Clustering algorithms Wireless sensor networks

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Analysis of Operation Optimization of Gas Pipelines Based on Adaptive Genetic Algorithm

Analysis of Operation Optimization of Gas Pipelines Based on...

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international symposium on Information engineering and Electronic Commerce, IEEC

作者： Changjun Li Wenlong Jia Yi Yang Xia Wu School of Petroleum Engineering Southwest Petroleum University Chengdu China

A variety of processes are utilized for gas transmission. It is important to optimize the operation conditions of these processes to promote efficiency. The operation efficiency of pipeline systems is combined with the purchase and sale prices of gas, the quantity bought and sold of gas and the management costs. Aimed at the maximum operation efficiency, an operation optimization model of gas pipelines is established with consideration of quantity input (output) constraints of each node, operation pressure constraints of pipelines, compressor constraints, valve constraints and hydraulic constraints of the pipeline system. The model adapts to all kinds of pipeline structures and it is solved by the method of adaptive genetic algorithm because of its non-linear form. Based on this, a computer program is developed to optimize the operation conditions of gas trunk lines, gas gathering and distribution network. Finally, an application example is given.

关键词： Algorithm design and analysis Pipelines Genetic algorithms Marketing and sales Costs Constraint optimization Valves Computer networks distributed computing Application software

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