Fast track is a software speculation system that enables unsafe optimization of sequential code. It speculatively runs optimized code to improve performance and then checks the correctness of the speculative code by r...
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ISBN:
(纸本)9780769535760
Fast track is a software speculation system that enables unsafe optimization of sequential code. It speculatively runs optimized code to improve performance and then checks the correctness of the speculative code by running the original program on multiple processors. We present the interface design and system implementation for Fast Track. It lets a programmer or a profiling tool mark fast-track code regions and uses a run-time system to manage the parallel execution of the speculative process and its checking processes and ensures the correct display of program outputs. The core of the run-time system is a novel concurrent algorithm that balances exploitable parallelism and available processors when the fast track is too slow or too fast. The programming interface closely affects the run-time support. Our system permits both explicit and implicit end markers for speculatively optimized code regions as well as extensions that allow the use of multiple tracks and user defined correctness checking. We discuss the possible uses of speculative optimization and demonstrate the effectiveness of our prototype system by examples of unsafe semantic optimization and a general system for fast memory-safety checking, which is able to reduce the checking time by factors between 2 and 7 for large sequential code on a 8-CPU system.
Real-time transient stability simulation is of paramount importance for system security assessment and to initiate preventive control actions before catastrophic events such as blackouts happen. Transient stability si...
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ISBN:
(纸本)9781424444281
Real-time transient stability simulation is of paramount importance for system security assessment and to initiate preventive control actions before catastrophic events such as blackouts happen. Transient stability simulation of realisticsize power systems involves the solution of a large set of non-linear differential-algebraic equations in the time-domain which requires significant computational resources. Exploitation of parallel processing techniques can provide an efficient and cost-effective solution to this problem. This paper proposes a fully parallel method known as instantaneous relaxation (IR) for real-time transient stability simulation. To validate and evaluate the proposed method a test system has been implemented on a distributed PC-Cluster based real-time simulator. A comparison of the captured real-time results with those from the PSS/E software shows high accuracy.
Security engineering has some features that are intrinsically different from software (reliability) engineering. Traditional softwareengineering environments are not adequate and effective for designing, developing, ...
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Security engineering has some features that are intrinsically different from software (reliability) engineering. Traditional softwareengineering environments are not adequate and effective for designing, developing, managing, and maintaining secure softwaresystems. This paper presents our development of ISEE, an information security engineering environment we are developing, that integrates various tools and provides comprehensive facilities to support design, development, management, and maintenance of security facilities of information/softwaresystems continuously and consistently, and guides and helps all users to perform their tasks regularly according to ISO/IEC security standards. ISEE is the first real information security engineering environment.
Common Component Architecture (CCA) is an emerging effort to bring Component-based softwareengineering (CBSE) to High Performance Computing (HPC). Many scientific applications may benefit from CBSE paradigm whose eff...
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This paper describes a service oriented programming platform for Internet-based Virtual Computing Environment (iVCE), which is targetted for enabling collaboration among autonomous entities over Internet. This platfor...
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Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embe...
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ISBN:
(纸本)9780769536422
Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embedded system design. The aim of this paper is to introduce accurate and efficient power metrics included in a hardware/software (HW/SW) co-design environment to show the system-level partitioning and design. In order to verify the design effectiveness of hardware/software co-design synthesis, we consider the digital power dissipation methodology and its power reduction techniques. To maximize the performance of system, we developed hierarchical design technique and co-design synthesis for power efficient HW/SW co-design process. In the end, we provided simulation results for single circuit with new design vs. circuit integration with hierarchical power efficiency system (HPES), multiple circuits with new design vs. circuit integration with HPES, new design and no load vs. circuit integration with HPES, new design with load vs. circuit integration with HPES.
Computing in financial services consists of a combination of time-critical computations completed during trading hours, such as Monte Carlo simulations for option pricing, and over-night calculations on massive data s...
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ISBN:
(纸本)9780387784168
Computing in financial services consists of a combination of time-critical computations completed during trading hours, such as Monte Carlo simulations for option pricing, and over-night calculations on massive data sets, such as those required for market risk measurement. To date, this has typically been done using traditional parallel or cluster computing techniques. The French National Research Agency (ANR), along with several banks and financial software companies have partnered with INRIA to explore the application of grid computing to this domain. The PicsouGrid project utilizes the ProActive Java distributed computing library to parallelize and distribute Monte Carlo option pricing simulations, concurrently utilizing 102-103 workers. PicsouGrid has been deployed on various grid systems to evaluate its scalability and performance. Issues arising from the heterogeneity and layering of grid infrastructures are addressed via an abstract process model which is applied at each layer. Timings of both the algorithms and the grid infrastructures are carefully measured to provide better insight into the behavior and utilization of computational grids for this important class of parallel simulations.
A new anomaly detection scheme based on growing structure multiple model system (GSMMS) is proposed in this paper to detect and quantify the effects of anomalies. The GSMMS algorithm combines the advantages of growing...
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A new anomaly detection scheme based on growing structure multiple model system (GSMMS) is proposed in this paper to detect and quantify the effects of anomalies. The GSMMS algorithm combines the advantages of growing self-organizing networks with efficient local model parameter estimation into an integrated framework for modeling and identification of general nonlinear dynamic systems. The identified model then serves as a foundation for building an effective anomaly detection and fault diagnosis system. By utilizing the information about system operation region provided by the GSMMS, the residual errors can be analyzed locally within each operation region. This local decision making scheme can accommodate for unequally distributed residual errors across different operational regions. The performance of the newly proposed method is evaluated through anomaly detection and quantification in an electronically controlled throttle system, which is simulated using a high-fidelity engine simulation software package provided by a major automotive manufacturer for control system development.
Network Processors (NPs) are attracting and powerful platforms for the fast development of high performance network applications. However, despite their greater flexibility and limited cost with respect to specialized...
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ISBN:
(纸本)1565553306
Network Processors (NPs) are attracting and powerful platforms for the fast development of high performance network applications. However, despite their greater flexibility and limited cost with respect to specialized hardware design, NP still face developers with significant difficulties. As they target complex and high-performance applications, programmers are often forced to write assembly code in order to better exploit the hardware. In this paper we propose an approach to NP programming which is based on a three-phase development methodology, and we apply it to Intel NPs of the IXP2XXX family. By exploiting a composition of software tools, a high-level definition of the application is turned first into a distributed program, then into an NP prototype, and finally into an efficient NP executable. The methodology we describe takes advantage of the ASSIST technology, which allows for the porting, testing, modeling and profiling of parallel applications on a cluster of standard PCs. We developed a C library that acts as a communication layer, hiding the hardware details of NP programming and allowing for high performance code development. The ultimate goal of this approach is to let programmers write C code, exploiting ASSIST-provided hints to (1) perform functional debugging and performance analysis and (2) to experiment with different parallel structures. The resulting code can be then directly compiled for the NP without modifications, largely reducing the overall coding effort.
Today's market demand for smaller, more powerful consumer electronics poses a major challenge to the rapid design of products. In addition, the ability to perform strategic coordination amongst different stakehold...
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