The goal of this paper is to find the best model for LEDs used in simulations for street lighting. The model of LED has three parameters: V_LED, I_LED and R_LED. First, it is presented a model of LED extracted from th...
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ISBN:
(纸本)9781479975143
The goal of this paper is to find the best model for LEDs used in simulations for street lighting. The model of LED has three parameters: V_LED, I_LED and R_LED. First, it is presented a model of LED extracted from the I-V characteristic given in the datasheet of producer. This model will be called MDS (Model from the Data Sheet). Secondly, for the same LED the I-V characteristic is raised through measurements. After the equation is established, the parameters of the LED are calculated with simple equations;this model is called MPM (Model Proposed from Measurements). The third model is obtained from averaging the measurements of parameters values for many series LEDs;this model is called MPA (Model Proposed from Averaging). All models are introduced in simulations. After that, the results are compared with the measurements. The errors obtained with the model proposed MPM are less than the errors obtained with the MDS and MPA model. This model is the best for simulations. The LED used in this paper is OSLON SSL 150 from OSRAM. The parameters of MDS are: V_LED=2.944V, I_LED=350mA and R_LED=555m Omega. The parameters of MPM are: V_LED=2.934V, I_LED=350mA and R_LED=642m Omega. The errors with the MDS are less than 13.33%, and with the MPM are less than 7.88%. The errors with the MPA are less than 25% For simulations and measurements is used the driver MP4021A from Monolithic Power systems (MPS) for two parallel strings of 16 series LEDs (32W). The software used is MPSmart 7.20 from MPS and for measurements are used Fluke 8808A digital multimeters.
Summary form only given. Many researches have been devoted to designing appropriate concurrency control algorithms for real-time database systems, which not only satisfy consistency requirements but also meet transact...
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ISBN:
(纸本)0769521320
Summary form only given. Many researches have been devoted to designing appropriate concurrency control algorithms for real-time database systems, which not only satisfy consistency requirements but also meet transaction timing constraints as much as possible. Optimistic concurrency control protocols have the nice properties of being nonblocking and deadlock-free, but they have the problems of late conflict detection and transaction restarts. Although the number of transaction restarts is reduced by dynamic adjustment of serialization order (DASO) in real-time database systems, it still has some unnecessary transaction restarts. We first propose a new method called dynamic adjustment of execution order (DAEO) and a new optimistic concurrency control algorithm based on DAEO, which can reduce the number of unnecessary restarts near to zero and outperforms the previous algorithms, and then discuss the experiments and the results.
Nowadays, directory-based cache coherence protocols have been the best choice in designing large-scaled CC-NUMA systems. Directory contains the shared information of all memory blocks in system. The number of copies o...
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Nowadays, directory-based cache coherence protocols have been the best choice in designing large-scaled CC-NUMA systems. Directory contains the shared information of all memory blocks in system. The number of copies of shared data in system and their distributing characteristics are deeply influenced by the characteristics of application programs. In this paper, a Markov chains model is built for the distributing pattern of shared data in CC-NUMA systems. It's proved that, the average number of cache copies of shared data is small in CC-NUMA systems. Especially, when the percentage of shared read operations in applications is lower than 80%, this number is less than 5.
As computational devices continue to advance, there are reasons to examine their foundations a little more deeply, and to ask whether there may not be something more to be found. The fundamental manner in which hardwa...
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As computational devices continue to advance, there are reasons to examine their foundations a little more deeply, and to ask whether there may not be something more to be found. The fundamental manner in which hardware and software interact is poorly understood, and yet there is little indication in the literature that this is being discussed or explored. In spite of our technological achievements, we are at a loss to precisely define the boundaries between hardware and software, and to describe the nature of their interface. This paper aims to raise some of the major issues and questions, to propose a hardware-information duality, and to suggest directions in which further research might be pursued.
As the incidence of faults in real Wireless Sensor Networks (WSNs) increases, fault injection is starting to be adopted to verify and validate their design choices. Following this recent trend, this paper presents a t...
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As the incidence of faults in real Wireless Sensor Networks (WSNs) increases, fault injection is starting to be adopted to verify and validate their design choices. Following this recent trend, this paper presents a tool, named AVR-INJECT, designed to automate the fault injection, and analysis of results, on WSN nodes. The tool emulates the injection of hardware faults, such as bit flips, acting via software at the assembly level. This allows to attain simplicity, while preserving the low level of abstraction needed to inject such faults. The potential of the tool is shown by using it to perform a large number of fault injection experiments, which allow to study the reaction to faults of real WSN software.
The reliable and fault tolerant computers are key to the success to aerospace, and communication industries where failures of the system can cause a significant economic impact and loss of life. Designing a reliable d...
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The reliable and fault tolerant computers are key to the success to aerospace, and communication industries where failures of the system can cause a significant economic impact and loss of life. Designing a reliable digital system, and detecting and repairing the faults are challenging tasks in order for the digital system to operate without failures for a given period of time. The paper presents a new and systematic softwareengineering approach of performing fault diagnosis of digital systems, which have employed multiple processors. The fault diagnosis model is based on the classic PMC model to generate data obtained on the basis of test results performed by the processors. The PMC model poses a tremendous challenge to the user in doing fault analysis on the basis of test results performed by the processors. This paper will perform one fault model for developing software. The effort has been made to preserve the necessary and sufficient.
Chip multiprocessors (CMPs) and simultaneous multithreading (SMT) processors provide high performance but put more pressure on the memory interface than their single-thread counterparts. The "memory wall" pr...
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Chip multiprocessors (CMPs) and simultaneous multithreading (SMT) processors provide high performance but put more pressure on the memory interface than their single-thread counterparts. The "memory wall" problem is exacerbated by multiple threads sharing a memory interface, and will get worse as more cores are added. Therefore, communications between cores, using shared caches or fast interconnects between private caches, are needed to keep the CPUs busy without burdening the memory interface. Multiple CMP systems add another dimension to this challenging problem, as the communication mechanism is no longer uniform. To parallelize data-intensive applications for high performance on these systems, one must explore a number of execution behaviors in a complex architecture-dependent exercise that entails identifying key components of the communication subsystem and understanding their behavior under varying workloads. As part of ongoing research into efficient program execution models for parallel microprocessors, we have developed a tool to evaluate the performance of the storage controllers at different levels of the memory hierarchy under varying workloads and measure cache coherence overhead. The tool allows exploration of architectural features of real processors that affect the performance of several parallel execution approaches. Here, we demonstrate its use by evaluating two of our parallel programming models that employ architecture-specific optimizations and compare them to a conventional model for several applications on parallel microprocessors.
The first part of the paper describes a specialized multiprocessor environment for hybrid coding of visual communications signals in the range from ISDN basic access to primary rate transmission channels. Most importa...
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ISBN:
(纸本)0819402389
The first part of the paper describes a specialized multiprocessor environment for hybrid coding of visual communications signals in the range from ISDN basic access to primary rate transmission channels. Most important is a proprietary 4-wide SIMD parallel video processor with 80 MIPS. The second part deals with the software philosophy of the codec. It uses preanalysis and prebuffering in the first phase of coding a frame. In the second phase, limited processing power and available channel bits are distributed optimally over time and over changed areas of one frame. Codec delay is halved with respect to conventional codecs.
Scheduling on client-server systems has not received much attention from researchers. Based on simulation this research presents a number of insights into system behavior and scheduling. Two phenomena, CPU monopolizat...
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Scheduling on client-server systems has not received much attention from researchers. Based on simulation this research presents a number of insights into system behavior and scheduling. Two phenomena, CPU monopolization by large service requests and software bottlenecking are observed to have a strong influence on system performance. software bottlenecking is a new phenomenon, observed on distributed client server systems with multiple levels of servers and occurs when a higher level server is blocked waiting for a response to a service request from a lower level server. Policies based on request characteristics such as service times and path lengths are found to effectively control these effects and improve system performance.
The proceedings contain 18 papers. The topics discussed include: a software component model and its preliminary formalisation;synchronised hyperedge replacement as a model for service oriented computing;control of mod...
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ISBN:
(纸本)3540367497
The proceedings contain 18 papers. The topics discussed include: a software component model and its preliminary formalisation;synchronised hyperedge replacement as a model for service oriented computing;control of modular and distributed discrete-event systems;model-based security engineering with UML: introducing security aspects;the pragmatics of STAIRS;smallfoot: modular automatic assertion checking with separation logic;separation results via leader election problems;divide and congruence: from decomposition of modalities to preservation of branching bisimulation;abstraction and refinement in model checking;program compatibility approaches;cluster-based LTL model checking of large systems;safety and liveliness in concurrent pointer programs;modular specification of encapsulated object-oriented components;and on a probabilistic chemical abstract machine and expressiveness of Linda languages.
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