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检索条件"任意字段=International Symposium on Software Engineering for Parallel and Distributed Systems"

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Combating side-channel attacks using key management

Combating side-channel attacks using key management

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Donggang Liu Qi Dong ISec Laboratory Department of Computer Science and Engineering University of Texas Arlington USA

Embedded devices are widely used in military and civilian operations. They are often unattended, publicly accessible, and thus vulnerable to physical capture. Tamper-resistant modules are popular for protecting sensitive data such as cryptographic keys in these devices. However, recent studies have shown that adversaries can effectively extract the sensitive data from tamper-resistant modules by launching semi-invasive side-channel attacks such as power analysis and laser scanning. This paper proposes an effective key management scheme to harden embedded devices against side-channel attacks. This technique leverages the bandwidth limitation of side channels and employs an effective updating mechanism to prevent the keying materials from being exposed. This technique forces attackers to launch much more expensive and invasive attacks to tamper embedded devices and also has the potential of defeating unknown semi-invasive side-channel attacks.

关键词： Hardware Data mining Wireless sensor networks Information security Laboratories Protection Power lasers Optical materials Sensor systems Control systems

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Multithreading-Enabled Active Replication for Event Stream Processing Operators

Multithreading-Enabled Active Replication for Event Stream P...

引用

Reliable distributed systems

作者： Andrey Brito Christof Fetzer Pascal Felber Systems Engineering Group Technische Universität Dresden Dresden Germany Institut d'informatique University of Neuchâtel Neuchatel Switzerland

Event stream processing (ESP) systems are very popular in monitoring applications. Algorithmic trading, network monitoring and sensor networks are good examples of applications that rely upon ESP systems. As these systems become larger and more widely deployed, they have to answer increasingly stronger requirements that are often difficult to satisfy. Fault-tolerance is a good example of such a non-trivial requirement. Making ESP operators fault-tolerant can add considerable performance overhead to the application. In this paper, we focus on active replication as an approach to provide fault-tolerance to ESP operators. More precisely, we address the performance costs of active replication for operators in distributed ESP *** use a speculation mechanism based on software transactional memory (STM) to achieve the following goals: (i) enable replicas to make progress using optimistic delivery; (ii) enable early forwarding of speculative computation results; (iii) enable active replication of multi-threaded operators using transactional executions. Experimental evaluation shows that, using this combination of mechanisms, one can implement highly efficient fault-tolerant ESP operators.

关键词： Electrostatic precipitators Fault tolerance Monitoring Delay Application software Costs Broadcasting Reliability engineering systems engineering and theory Sensor systems and applications

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Efficient scheduling of task graph collections on heterogeneous resources

Efficient scheduling of task graph collections on heterogene...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Matthieu Gallet Loris Marchal Frederic Vivien Université de Lyon France LIP laboratory UMR ENS Lyon-CNRS-INRIA-UCBL Lyon France INRIA France

In this paper, we focus on scheduling jobs on computing grids. In our model, a grid job is made of a large collection of input data sets, which must all be processed by the same task graph or workflow, thus resulting in a collection of task graphs problem. We are looking for a competitive scheduling algorithm not requiring complex control. We thus only consider single-allocation strategies. In addition to a mixed linear programming approach to find an optimal allocation, we present different heuristic schemes. Then, using simulations, we compare the performance of our different heuristics to the performance of a classical scheduling policy in Grids, HEFT. The results show that some of our static-scheduling policies take advantage of their platform and application knowledge and outperform HEFT, especially under communication-intensive scenarios. In particular, one of our heuristics, DELEGATE, almost always achieves the best performance while having lower running times than HEFT.

关键词： Processor scheduling Grid computing Scheduling algorithm distributed computing Application software Laboratories Linear programming Steady-state Large-scale systems Physics

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How to build programmable multi-core chips

How to build programmable multi-core chips

引用

IEEE symposium on High-Performance Computer Architecture

作者： Jack Dennis Electrical Engineering MIT-CSAIL USA

The arrival of multi-core chips has heightened interest in the discipline of parallel programming, a topic that has received much attention for many years. Computer architects have much to learn from sound principles for structuring software and expressing parallel computation. This talk will cover principles for the design of computer systems to support composable parallel software - the idea that any parallel program is usable, without change, as a component of larger parallel programs. By following these principles, a revolution in the ease of building robust and high-performance parallel software can be achieved. The principles suggest interesting directions for computer architecture; the tools to experiment with new architecture concepts are ready and waiting for the savvy and ambitious researcher.

关键词： Computer architecture Mathematical programming Concurrent computing Lifting equipment Computer languages parallel programming Buildings Robustness Writing Quadratic programming

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A Method of In-Depth-Defense for Network Security Based on Immunity Principles

A Method of In-Depth-Defense for Network Security Based on I...

引用

international symposium on parallel and distributed Processing with Applications, ISPA

作者： Yaping Jiang Jianhua Zhou Yong Gan Zengyu Cai School of Computer and Communication Engineering Zhengzhou University of Light Industry China

The concepts of self, nonself, antibody, antigen and vaccine in in-depth-defense system for network security was presented in this paper, the architecture of in-depth defense for network intrusion and detection based on immune principle is proposed. The intrusion information gotten from current monitored network is encapsulated and sent to the neighbor network as bacterin; therefore the neighbor network can make use of the bacterin and predict the danger of network. We can use communicate agent cooperated with response agent to achieve active defense formwork. The experimental results show that the new model not only actualizes an active prevention method but also improves the ability of intrusion detection and prevention than that of the traditional passive intrusion prevention systems.

关键词： Immune system Intrusion detection Humans Information security Packaging Communication system security Computer security Computer networks Vaccines Cloning

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Efficient Algorithms for Embedding Cycles in Augmented Cubes

Efficient Algorithms for Embedding Cycles in Augmented Cubes

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Hong-Chun Hsu Pao-Lien Lai Chang-Hsiung Tsai Tseng-Kuei Li Department of Medical Informatics Tzu Chi University Hualien Taiwan Department of Computer Science and Information Engineering National Dong Hwa University Shoufeng Hualien Taiwan Department of Computer Science and Information Engineering Ching Yun University of Technology Jungli Taiwan

Many parallel and distributed algorithms have been developed using such regular data structure as linear arrays, rings, trees, and meshes on hypercube-type interconnection networks. The augmented cube AQ n , proposed by Choudum and Sunitha, is a derivative of hypercubes with good geometric nature and retains all the favorable properties of the hypercube. The pancyclic properties of the n-dimensional augmented cube, AQ n , has attracted a lot of interest. In this paper, we introduce the augmented Gray code, AGC, and use AGC to construct cycles of arbitrary number of vertices into the augmented cube for any specific edge.

关键词： Reflective binary codes Hypercubes Multiprocessor interconnection networks Computer science Biomedical engineering Biomedical informatics distributed algorithms Tree data structures Computer networks Concurrent computing

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USGPA: A User-Centric and Secure Grid Portal Architecture for High-Performance Computing

USGPA: A User-Centric and Secure Grid Portal Architecture fo...

引用

international symposium on parallel and distributed Processing with Applications, ISPA

作者： Rongqiang Cao Xuebin Chi Zongyan Cao Zhihui Dai Haili Xiao Super Computing Center Computer Network Information Center Chinese Academy and Sciences Beijing China

A grid portal is one of the most important ways to access grid systems. The disadvantages existing in current grid portals are that they are designed for specific applications, difficult to add new applications. Besides, the security issues are not considered fully in these portals. In this paper, we proposed a user-centric and secure grid portal architecture-USGPA based on portlet. In USGPA, a security portlet model is proposed in which security issues for sensitive data and the portal server are solved. Based on the model, the application portlet model is proposed with which new applications can be encapsulated into portal quickly. Then all portlets for high-performance computing-HPC are designed based on these two models. With these portlets, users can not only manage jobs via portal but also can custom the portal by selecting and managing the applications they required. Last but important, a prototype is implemented to evaluate the scalability, security and efficiency of the architecture.

关键词： Portals Computer architecture Grid computing Application software Data security Biology computing Computer networks Supercomputers Concurrent computing distributed computing

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Accelerating HMMer on FPGAs using systolic array based architecture

Accelerating HMMer on FPGAs using systolic array based archi...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Yanteng Sun Peng Li Guochang Gu Yuan Wen Yuan Liu Dong Liu College of Computer Science and Technology Harbin Engineering of Technology China Intel China Research Center Limited China

HMMer is a widely-used bioinformatics software package that uses profile HMMs (Hidden Markov Models) to model the primary structure consensus of a family of protein or nucleic acid sequences. However, with the rapid growth of both sequence and model databases, it is more and more time-consuming to run HMMer on traditional computer architecture. In this paper, the computation kernel of HMMer, P7Viterbi, is selected to be accelerated by FPGA. There is an infrequent feedback loop in P7Viterbi to update the value of beginning state (B state), which limits further parallelization. Previous work either ignored the feedback loop or serialized the process, leading to loss of either precision or efficiency. Our proposed syslolic array based architecture with a parallel data providing unit can exploit maximum parallelism of the full version of P7Viterbi. The proposed architecture speculatively runs with fully parallelism assuming that the feedback loop does not take place. If the rare feedback case actually occurs, a rollback mechanism is used to ensure correctness. Results show that by using Xilinx Virtex-5 110T FPGA, the proposed architecture with 20 PEs can achieve about a 56.8 times speedup compared with that of Intel Core2 Duo 2.33 GHz CPU.

关键词： Acceleration Field programmable gate arrays Systolic arrays Hidden Markov models Feedback loop Computer architecture parallel processing Bioinformatics software packages Proteins

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Using GPU to Accelerate Cache Simulation

Using GPU to Accelerate Cache Simulation

引用

international symposium on parallel and distributed Processing with Applications, ISPA

作者： Wan Han Gao Xiaopeng Wang Zhiqiang Li Yi State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beijing Aeronautics and Astronautics University Beijing China

Caches play a major role in the performance of high speed computer systems. Trace driven simulator is the most widely used method to evaluate cache architectures. However, as the cache design moves to more complicated architectures, along with the size of the trace is becoming larger and larger. Traditional simulation methods are no longer practical due to their long simulation cycles. Several techniques have been proposed to reduce the simulation time of sequential trace driven simulation. This paper considers the use of generic GPU to accelerate cache simulation which exploits set partitioning as the main source of parallelism. We develop more efficient parallel simulation techniques by introducing more knowledge into the Compute Unified Device Architecture (CUDA) on the GPU. Our experimental result shows that the new algorithm gains 2.76 times performance improvement compared to traditional CPU based sequential algorithm.

关键词： Acceleration Computational modeling Computer architecture Analytical models Concurrent computing Computer simulation High performance computing parallel processing parallel algorithms distributed processing

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Photo retrieval based on spatial layout with hardware acceleration

Photo retrieval based on spatial layout with hardware accele...

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IEEE international symposium on Intelligent Signal Processing and Communication systems (ISPACS)

作者： Tse-Wei Chen Yi-Ling Chen Shao-Yi Chien Media IC and System Laboratory Graduate Institute of Electronics Engineering and Department of Electrical Engineering National Taiwan University Taipei Taiwan

A new photo retrieval system for mobile devices is proposed in this paper. The system can be used to search for photos with similar spatial layout effectively and efficiently, and it adopts a new algorithm that extracts features of image regions based on hardware K-Means clustering. Since K-Means is computationally intensive for real-time applications in embedded systems, it is necessary to accelerate K-Means using parallel architecture to meet the real-time requirement of the retrieval process. Experiments show that the proposed algorithm in the photo retrieval system obtains better mean average precision than other methods, and the K-Means hardware provides a tradeoff between the execution time and the retrieval performance on the software and hardware co-simulation platform with an FPGA.

关键词： Hardware Acceleration Clustering algorithms Real time systems Feature extraction Concurrent computing Embedded computing Embedded system parallel architectures software algorithms

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