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检索条件"任意字段=International Symposium on Software Engineering for Parallel and Distributed Systems"

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DAGGER: a novel generic methodology for FPGA bitstream generation and its software tool implementation

DAGGER: a novel generic methodology for FPGA bitstream gener...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： K. Siozios G. Koutroumpezis K. Tatas D. Soudris A. Thanailakis VLSI Design Laboratory Department Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece

A novel bitstream generation algorithm and its software implementation are introduced. Although this tool was developed for the configuration of AMDREL FPGA reconfigurable platform, it could be used to program any other compatible device. This tool is the only one known academic implementation for FPGA configuration with such features. Among them are the run-time-, partial- and dynamic-reconfiguration, the memory management, the bitstream compression and encryption, the read-back technique, the bitstream reallocation, the used low-power techniques as well as the graphical user interface.

关键词： Field programmable gate arrays software tools Design automation Runtime Hardware Logic functions Very large scale integration software algorithms Memory management Cryptography

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JEOPARD -- Java Environment for parallel Real-Time Development

JEOPARD -- Java Environment for Parallel Real-Time Developme...

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international symposium on Object-Oriented Real-Time distributed Computing

作者： Fridtjof Siebert Aicas GmbH Karlsruhe Germany

Multicore systems have become standard for desktop computers today. Current operating systems and software development tools provide straightforward means to use the additional computing power. However, a more fundamental change in the design and development of software is required to fully exploit the power of multicore systems. Furthermore, the fast growing market of embedded systems is currently largely unaffected by the introduction of multicore systems. This will change quickly in the future, which will mean that there will be a demand on efficient development of reliable embedded software that can give real-time guarantees and exploit the available power on multicore *** JEOPARD project addresses this demand by developing Java software tools to exploit multicore power while ensuring correctness and predictable timing. This paper gives an overview of the JEOPARD project and focuses on key technical issues such as real-time scheduling and real-time garbage collection on multi-core systems.

关键词： Java Multicore processing Real time systems Power system reliability Operating systems Programming Embedded system Embedded software software tools Timing

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Development of the embry-riddle aeronautical university wave adaptive modular vessel as an integral part of a heterogeneous intelligent teaming system

Development of the embry-riddle aeronautical university wave...

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AUVSI XPONENTIAL 2017

作者： Zuercher, Tim Coyle, Eric Currier, Patrick Mechanical Engineering Embry-Riddle Aeronautical University 600 S. Clyde Morris Blvd. Daytona BeachFL32114 United States

Embry-Riddle Aeronautical University (ERAU) is one of three schools from the United States to have participated in the Maritime RobotX Challenge in both 2014, in Singapore, and 2016, Honolulu. The 2016 challenge, sponsored by the Office of Naval Research and the Association for Unmanned systems international Foundation, requires teams to develop a fully-autonomous surface vehicle based on the 16-foot high-performance Wave Adaptive Modular Vessel (WAM-V) platform. The platform must accomplish multiple complex interrelated tasks without any user interaction. These tasks include buoy channel navigation, docking, target recognition, sonar localization, and the launch and recovery of an autonomous sub vehicle. The system architecture developed for the ERAU WAM-V platform consists of multiple software nodes running in parallel to produce the complex behaviors required by the RobotX Challenge. These nodes include a sensor fusion probabilistic perception suite, state estimation, health monitoring, mission planning, and trajectory planning. This coupled with the modular mounting system, allows for the installation of mission specific software and hardware with little if any modification to mission critical hardware. One end goal of this software and mechanical approach is the development of the ERAU WAM-V platform as part of a heterogeneous intelligent team of autonomous systems, varying from maritime assets to unmanned aircraft to ground vehicles, all capable of completing complex distributed tasks. This paper discusses the challenges in developing the ERAU RobotX platform including an overview of the competition tasks, the modular hardware design, and the software architecture, as well as how these fit into the overall teaming scheme. Perception, guidance, navigation and control autonomy algorithms will be discussed, as well as the modular nature of the platform and its integration with other autonomous platforms.

关键词： Fighter aircraft

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The Tuple Channel coordination model

The Tuple Channel coordination model

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IEEE international Workshop on software engineering for parallel and distributed systems

作者： M. Diaz B. Rubio J.M. Troya Dpto. Lenguajes y Ciencias de la Computación Universidad de Málaga Malaga Spain

We present a new coordination model and a small set of programming notations for distributed programming that can be integrated into very different programming languages (imperative, declarative or object oriented). Both together, allow distributed programs to be developed in a compositional way, by assembling different independent pieces of (possibly preexisting and heterogeneous) code. This approach is in the spirit of many other similar proposals, such as Linda, supporting multiparadigm and multilingual integration. In addition, the Tuple Channel coordination model provides a powerful set of concurrent programming techniques, inherited from concurrent logic languages (CLLs), but trying to overcome the efficiency drawbacks of logic variables in distributed implementations of CLLs. We introduce this coordination model, giving some illustrative examples to show its suitability and expressiveness; some implementation issues are also commented on.

关键词： Object oriented modeling Proposals Logic programming distributed computing Object oriented programming Computational modeling Computer languages Assembly software engineering Buildings

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Hypergraph-based task-bundle scheduling towards efficiency and fairness in heterogeneous distributed systems

Hypergraph-based task-bundle scheduling towards efficiency a...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Han Zhao Xinxin Liu Xiaolin Li Scalable Software Systems Laboratory Department of Computer Science Oklahoma State University Stillwater OK USA

ISBN: (纸本)9781424464425

This paper investigates scheduling loosely coupled task-bundles in highly heterogeneous distributed systems. Two allocation quality metrics are used in pay-per-service distributed applications: efficiency in terms of social welfare, and fairness in terms of envy-freeness. The first contribution of this work is that we build a unified hypergraph scheduling model under which efficiency and fairness are compatible with each other. Second, in the scenario of budget-unawareness, we formulate a strategic algorithm design for distributed negotiations among autonomous self-interested computing peers and prove its convergence to complete local efficiency and envy-freeness. Third, we add budget limitation to the allocation problem and propose a class of hill-climbing heuristics in favor of different performance metrics. Finally we conduct extensive simulations to validate the performance of all the proposed algorithms. The results show that the decentralized hypergraph scheduling method is scalable, and yields desired allocation performance in various scenarios.

关键词： Processor scheduling Job shop scheduling Peer to peer computing distributed computing Environmental economics Game theory Application software Computational modeling Cloud computing Grid computing

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Enhanced State History Tree (eSHT) : a Stateful Data Structure for Analysis of Highly parallel System Traces 5

Enhanced State History Tree (eSHT) : a Stateful Data Structu...

引用

IEEE international Congress on Big Data (BigData Congress)

作者： Prieur-Drevon, Loic Beamonte, Raphael Ezzati-Jivan, Naser Dagenais, Michel R. Ecole Polytech Montreal Dept Comp Engn Montreal PQ Canada

ISBN: (纸本)9781509026227

Behaviors of distributed systems with many cores and/or many threads are difficult to understand. This is why dynamic analysis tools such as tracers are useful to collect run-time data and help programmers debug and optimize complex programs. However, manual trace analysis on very large traces with billions of events can be a difficult problem which automated trace visualizers and analyzers aim to solve. Trace analysis and visualization software needs fast access to data which it cannot achieve by searching through the entire trace for every query. A number of solutions have adopted stateful analysis which rearranges events into a more query friendly structures after a single pass through the trace. In this paper, we look into current implementations and model the behavior of previous work, the State History Tree (SHT), on traces with many thread creation and deletion. This allows us to identify which properties of the SHT are responsible for inefficient disk usage and high memory consumption. We then propose a more efficient data structure, the enhanced State History Tree (eSHT), to store and query computed states, in order to limit disk usage and reduce the query time for any state. Next, we compare the use of SHT and eSHT on traces with many attributes. We finally verify the scalability of our new data structure according to trace size. As shown by our results, the proposed solution makes near optimal use of disk space, reduces the algorithm's memory usage logarithmically for previously problematic cases, and speeds up queries on traces with many attributes by an order of magnitude. The proposed solution builds upon our previous work, enabling it to easily scale up to traces containing a million threads.

关键词： Data structure distributed History tree Multi-dimensional indexes parallel State system Stateful analysis Tracing

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A design flow tailored for self dynamic reconfigurable architecture

A design flow tailored for self dynamic reconfigurable archi...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Fabio Cancare Marco D. Santambrogio Donatella Sciuto Dipartimento di Elettronica e Informazione Politecnico di Milano Milan Italy

Dynamic reconfigurable embedded systems are gathering, day after day, an increasing interest from both the scientific and the industrial world. The need of a comprehensive tool which can guide designers through the whole implementation process is becoming stronger. In this paper the authors introduce a new design framework which amends this lack. In particular the paper describes the entire low level design flow onto which the framework is based.

关键词： Reconfigurable architectures Field programmable gate arrays Embedded system High performance computing Hardware Application software Runtime Engines Coprocessors software architecture

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Energy aware algorithmic engineering 22

Energy aware algorithmic engineering

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2014 22nd Annual IEEE international symposium on Modeling, Analysis and Simulation of Computer, and Telecommunication systems, MASCOTS 2014

作者： Roy, Swapnoneel Rudra, Atri Verma, Akshat School of Computing University of North Florida JacksonvilleFL32224 United States Department of CSE University at Buffalo SUNY BuffaloNY14260 United States IBM Research - India New Delhi India

ISBN: (纸本)9781479956104

In this work, we argue that energy management should be a guiding principle for design and implementation of algorithms. Traditional complexity models for algorithms are simple and do not aid in design of energy-efficient algorithms. In this work, we conducted a large number of experiments to understand energy consumption for algorithms. We study the energy consumption for popular vector operations, matrix operations, sorting, and graph algorithms. We observed that the energy consumption for any given algorithm depends on the memory parallelism the algorithm can exhibit for a given data layout in the RAM with variations up to 100% for many popular algorithms. Our experiments validate the asymptotic energy complexity model presented in a companion paper [1] and brings out many practical insights. We show that reads can be more expensive in terms of energy than writes, and different data types can lead to different energy consumption. Our most important result is a theoretical and experimental quantification of the impact of parallel data sequences on energy consumption. We also observe that high memory parallelism can also increase energy consumption with multiple concurrent access sequences. We use insights from our experiments to propose algorithmic engineering techniques for practical energy efficient software. © 2014 IEEE.

关键词： Energy utilization

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MultiPADDI-2 board for image processing

MultiPADDI-2 board for image processing

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Conference on parallel and distributed Methods for Image Processing

作者： Srini, VP Chow, N Sutton, RA Rabaey, JM Data Flux Systems Inc. MS 292 Berkeley CA 94709 1678 Shattuck Ave. United States University of California EECS Dept. Berkeley CA 94720 United States

ISBN: (纸本)0819425885

We have constructed a prototype image processing board containing 384 processors In 8 VLSI chips. The goal of the prototype is to show how fine grain parallelism present in image processing applications can be exploited by using lots of simple processors inter-connected in clever ways. Each processor has a 16-bit data path, a simple instruction set containing 12 instructions, a simple control unit, and a scan chain for loading data and program, Each VLSI chip, called PADDI-2, contains 48 processors, The programming model used for the processors is MIMD. Each processor has 8 words in the instruction memory. There are internal registers and queues in a processor for storing data and partial results. Data is assumed to be entering the system as a stream and processed by the processors. Each VLSI chip is connected to an external memory (64K x 16). a hardware synchronization mechanism is used for communication between processors;memory, and the external environment. If a sender and receiver is within the same chip, communication can be done in one cycle by the hierarchical interconnect bus structure, Programming the processors and the interconnections are done at compile time. The board is interfaced to a Sun SPARCstation using the SBus. Video input and output is supported by the board and field buffers are used for buffering. software tools for checking the board, running test programs at the assembly language level, and Libraries for application development have been produced. Image processing applications are currently under development. The board is available for experimentation over the Internet. Further details are available from the project web page (http://***/spartan).

关键词： parallel DSP image processing data driven processor data streaming

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Service-Oriented Computing - ICSOC 2012 Workshops 1

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丛书名： Lecture Notes in Computer Science

1000年

作者： Aditya Ghose Huibiao Zhu Qi Yu Alex Delis Quang Z. Sheng Olivier Perrin Jianmin Wang Yan Wang

ISBN: (数字)9783642378041

ISBN: (纸本)9783642378034

This book constitutes the thoroughly refereed proceedings of the 2012 ICSOC Workshops consisting of 6 scientific satellite events, organized in 3 main tracks including workshop track (ASC, DISA. PAASC, SCEB, SeMaPS and WESOA 2012), PhD symposium track, demonstration track; held in conjunction with the 10th international Conference on Service-Oriented Computing (ICSOC), in Shanghai, China, November 2012. The 53 revised papers presents a wide range of topics that fall into the general area of service computing such as business process management, distributed systems, computer networks, wireless and mobile computing, grid computing, networking, service science, management science, and software engineering.

关键词： software engineering Information systems Applications (incl. Internet) IT in Business Computer Appl. in Administrative Data Processing Management of Computing and Information systems Computer Imaging, Vision, Pattern Recognition and Graphics

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