Event stream applications consist of an acyclic graph of components that are traversed by streams of events. Examples of operations in such components are filtering, aggregation, enrichment, and transformation of even...
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ISBN:
(纸本)9781605583617
Event stream applications consist of an acyclic graph of components that are traversed by streams of events. Examples of operations in such components are filtering, aggregation, enrichment, and transformation of events and, commonly, applications include a mix of common-use library functions and user-defined functions. When the operation only depends on the current input events, the component can be trivially parallelized by replication. However, if the component keeps state that is used for the computation of the results, the trivial parallelization approach does not work. parallel versions for common components have being designed, but complex or user-defined components are normally limited by single thread performance. In this work, we use optimistic parallelization approaches to harness the potential of multi-core processors to scale the performance of stateful operators in event stream applications. In addition, we investigate indulgent ways to allow the user to provide application knowledge that can improve the amount of useful speculative work. The current prototype shows considerable gain in throughput even though some speculative executions must be disregarded. Copyright 2008 ACM.
Many large-scale production applications often have very long executions times and require periodic data checkpoints in order to save the state of the computation for program restart and/or tracing application progres...
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Many large-scale production applications often have very long executions times and require periodic data checkpoints in order to save the state of the computation for program restart and/or tracing application progress. These write-only operations often dominate the overall application runtime, which makes them a good optimization target. Existing approaches for write-behind data buffering at the MPI I/O level have been proposed, but challenges still exist for addressing system-level I/O issues. We propose a two-stage write-behind buffering scheme for handing checkpoint operations. The first-stage of buffering accumulates write data for better network utilization and the second-stage of buffering enables the alignment for the write requests to the file stripe boundaries. Aligned I/O requests avoid file lock contention that can seriously degrade I/O performance. We present our performance evaluation using BTIO benchmarks on both GPFS and Lustre file systems. With the two-stage buffering, the performance of BTIO through MPI independent I/O is significantly improved and even surpasses that of collective I/O.
Summary form only given. With the momentum gaining for the grid computing systems, the issue of deploying support for integrated scheduling and fault-tolerant approaches becomes paramount importance. Unfortunately, fa...
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Summary form only given. With the momentum gaining for the grid computing systems, the issue of deploying support for integrated scheduling and fault-tolerant approaches becomes paramount importance. Unfortunately, fault-tolerance has not been factored into the design of most existing grid scheduling strategies. To this end, we propose a fault-tolerant scheduling policy that loosely couples job scheduling with job replication scheme such that jobs are efficiently and reliably executed. Performance evaluation of the proposed fault-tolerant scheduler against a nonfault-tolerant scheduling policy is presented and shown that the proposed policy performs reasonably in the presence of various types of failures.
Symbiotic robotics is a discipline within collective robotics that is concerned with artificial multi-cellular robot-organisms that define their morphological structure by aggregation through self-assembling and they ...
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The paper addresses the build problem in the HPC arena that results from heterogeneity in hardware architectures, system software, and application build systems. We propose a new approach that generalizes current buil...
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The paper addresses the build problem in the HPC arena that results from heterogeneity in hardware architectures, system software, and application build systems. We propose a new approach that generalizes current build systems, and enhances their portability across heterogeneous high-end platforms. Although the original application build system needs to be modified it is a one-time activity that allows us to extract target platform specific information and store it into profiles. Our toolkit exploits profiles to retrieve appropriate target-specific information during the actual build process. Our developed mechanism termed late binding enables dynamic concretization of platform-specific variables from profiles. This approach simplifies the build process for heterogeneous environments, promotes profile reuse, and improves its portability. In order to verify our approach in practice we have applied our methodology to a production molecular dynamics code (the CPMD application).
Object-based storage is a storage architecture that manages data as objects, as opposed to other storage architectures like file systems which manage data as a file hierarchy and block storage which manages data as bl...
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jmpi is a 100% Java-based implementation of the message-passing interface (MPI-1) standard jmpi comes with an efficient and effective MPI implementation in Java and supports a user-friendly Java application programmin...
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jmpi is a 100% Java-based implementation of the message-passing interface (MPI-1) standard jmpi comes with an efficient and effective MPI implementation in Java and supports a user-friendly Java application programming interface (API) for MPI. We present the implementation details and give some early communication benchmark performance results on a cluster of SUN UltraSparc workstations.
Cloud computing, as a kind of internet-based computing, has to entrust data which are managed by external parties on remote servers. One of the critical security challenges on cloud computing is to ensure data securit...
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ISBN:
(纸本)9781509032051
Cloud computing, as a kind of internet-based computing, has to entrust data which are managed by external parties on remote servers. One of the critical security challenges on cloud computing is to ensure data security and privacy. In order to perform rigorous formal analysis for cloud-based applications, we use UML, an industry-adopted modeling language to build an abstraction of a system. In this paper, we extend class/profile diagram, sequence diagram and state diagram in UML 2.3 that contains sufficient information to model security protocols in cloud-based systems. Following that, a method is proposed to automatically translate UML models to pi calculus specification, which allows us to verify the data secrecy and confidentiality of security protocols using the existing protocol verifier - ProVerif. Our methodology is applied on ConfiChair, a security protocol in cloud computing system, to prove the effectiveness and feasibility of our approach.
In this paper we consider the problem of data collection from a sensor web consisting of N nodes, where nodes have packets of data in each round of communication that need to be gathered and fused with other nodes'...
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Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative nature of the computation, the most ener...
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Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative nature of the computation, the most energy-efficient execution in each processor may not translate into the most energy-efficient overall execution. We present the thrifty barrier, a hardware-software approach to saving energy in parallel applications that exhibit barrier synchronization imbalance. Threads that arrive early to a thrifty barrier pick among existing low-power processor sleep states based on predicted barrier stall time and other factors. We leverage the coherence protocol and propose small hardware extensions to achieve timely wake-up of these dormant threads, maximizing energy savings while minimizing the impact on performance.
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