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BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling

BZSim: Fast, Large-Scale Microarchitectural Simulation with ...

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IEEE international symposium on Performance Analysis of systems and software

作者： Panagiotis Strikos Ahsen Ejaz Ioannis Sourdis Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

ISBN: (数字)9798350376388

ISBN: (纸本)9798350376395

Modeling of on-chip interconnects in microarchitectural simulations is becoming more important. Chips continue to increase their number of cores, i.e., via 3D stacking and multi-chiplet integration, and their performance is gradually more affected by their network. However, existing simulation alternatives are either too slow for large systems or lack support for modeling interconnects, which is on its own a computationally intensive task. This work offers an open-source solution that integrates an accurate, widely used network simulator into an existing fast, parallel microarchitectural simulator enhanced with a new mechanism to make network modeling lightweight. It is based on the observation that a significant fraction of the network traffic has low contention and on the conjecture that the latency of such traffic can be calculated analytically with good accuracy. The proposed approach offers a mechanism to detect low contention traffic and analytically calculate its latency reducing the overheads of network simulation. In essence, it offers a knob for trading simulation accuracy for speed. This tradeoff is explored by demonstrating 2-4× faster simulations within 3-5% error in normalized IPC and 10-20% in average packet latency. Our simulation setup is an order of magnitude faster than an optimistic gem5 setup with point-to-point interconnects and 3× slower than a ZSim setup without network modeling. Our approach is further used to assess the impact of Networkon-Chip designs on system performance and shows that a 32-core system is on average 1.2× faster when using the current state of the art NoC instead of a baseline NoC.

关键词： Analytical models Accuracy Microarchitecture Three-dimensional displays Computational modeling System performance Stacking

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Removing Image Artifacts From Scratched Lens Protectors

Removing Image Artifacts From Scratched Lens Protectors

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IEEE international symposium on Circuits and systems (ISCAS)

作者： Yufei Wang Renjie Wan Wenhan Yang Bihan Wen Lap-Pui Chau Alex C. Kot School of Electrical and Electronic Engineering Nanyang Technological University Singapore Department of Computer Science Hong Kong Baptist University Hong Kong Distributed High Performance Software Fundamental Research Laboratory Pengcheng National Lab China Department of Electronic and Information Engineering Hong Kong Polytechnic University Hong Kong

A protector is placed in front of the camera lens for mobile devices to avoid damage, while the protector itself can be easily scratched accidentally, especially for plastic ones. The artifacts appear in a wide variety of patterns, making it difficult to see through them clearly. Removing image artifacts from the scratched lens protector is inherently challenging due to the occasional flare artifacts and the co-occurring interference within mixed artifacts. Though different methods have been proposed for some specific distortions, they seldom consider such inherent challenges. In our work, we consider the inherent challenges in a unified framework with two cooperative modules, which facilitate the performance boost of each other. We also collect a new dataset from the real world to facilitate training and evaluation purposes. The experimental results demonstrate that our method outperforms the baselines qualitatively and quantitatively. The code and datasets will be released at https://***/wyf0912/flare-removal

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An Optical Transceiver Reliability Study based on SFP Monitoring and OS-level Metric Data

An Optical Transceiver Reliability Study based on SFP Monito...

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： Paolo Notaro Qiao Yu Soroush Haeri Jorge Cardoso Michael Gerndt Huawei Technologies Duesseldorf GmbH Munich Germany Chair of Computer Architecture and Parallel Systems Technical University of Munich Germany Chair of Distributed and Operating Systems Technical University of Berlin Germany Department of Informatics Engineering/CISUC University of Coimbra Portugal

The increasing demand for cloud computing drives the expansion in scale of datacenters and their internal optical network, in a strive for increasing bandwidth, high reliability, and lower latency. Optical transceivers are essential elements of optical networks, whose reliability has not been well-studied compared to other hardware components. In this paper, we leverage high quantities of monitoring data from optical transceivers and OS-level metrics to provide statistical insights about the occurrence of optical transceiver failures. We estimate transceiver failure rates and normal operating ranges for monitored attributes, correlate early-observable patterns to known failure symptoms, and finally develop failure prediction models based on our analyses. Our results enable network administrators to deploy early-warning systems and enact predictive maintenance strategies, such as replacement or traffic re-routing, reducing the number of incidents and their associated costs.

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FlowEmbed: Binary function embedding model based on relational control flow graph and byte sequence

FlowEmbed: Binary function embedding model based on relation...

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international Conference on parallel and distributed systems (ICPADS)

作者： Yongpan Wang Chaopeng Dong Siyuan Li Fucai Luo Renjie Su Zhanwei Song Hong Li Institute of Information Engineering Chinese Academy of Sciences China School of Cyber Security University of Chinese Academy of Sciences China State Grid Fujian Electric Power Company China

Binary function embedding models are applicable to various downstream tasks within IoT device software systems and have demonstrated advantages in numerous binary analysis tasks, such as vulnerability (homologous) function search and compilation optimization option identification. However, current binary function embedding methods either learn embedding based on code sequence, which lack the program semantics of functions (e.g., control flow, etc.) or based on program structure graphs, which omit global sequential information. As a result, these methods fall short in enabling models to learn the complete semantic of function. In this paper, we introduce FlowEmbed, a novel approach that synergistically integrates control flow and global semantic learning to facilitate exhaustive code comprehension. Initially, FlowEmbed harnesses a distinct relational control flow graph combined with the power of BERT and RGCN models to aptly capture the nuances of control flow semantics. Moreover, by deploying the DPCNN model on a byte sequence constructed from function machine code, FlowEmbed adeptly discerns the inherent global sequential semantics of binary functions. Through rigorous evaluations spanning three IoT-related tasks, FlowEmbed’s efficacy becomes evident, showcasing notable improvements: a 20.6% improvement in compilation optimization option identification, a 1.8% improvement in binary function similarity analysis, and an 11.9% improvement in homologous function search. Collectively, these results underscore FlowEmbed’s superior capability, positioning it as a invaluable asset in a binary analysis application.

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Automating Pipelines of A/B Tests with Population Split Using Self-Adaptation and Machine Learning

Automating Pipelines of A/B Tests with Population Split Usin...

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SEAMS international Workshop on software engineering for Adaptive and Self-Managing systems, ICSE

作者： Federico Quin Danny Weyns KU Leuven Leuven Belgium Linnaeus University Sweden KU Leuven Belgium

ISBN: (数字)9798400705854

ISBN: (纸本)9798350363838

A/B testing is a common approach used in industry to facilitate innovation through the introduction of new features or the modification of existing software. Traditionally, A/B tests are administrated manually and conducted sequentially, with each experiment targeting the entire population that uses the corresponding application. This approach can be time-consuming and costly, particularly when the experiments are not relevant to the entire population. To tackle these problems, we present a new self-adaptive approach called AutoPABS, short for Automated Pipelines of A/B tests using Self-adaptation. AutoPABS contributes: (1) a self-adaptive architecture that enables automated execution of A/B testing pipelines, (2) a population split component that is managed by the managing system of the self-adaptive architecture to enable more efficient A/B testing pipeline execution, and (3) a notation to specify A/B testing pipelines that can be executed using the self-adaptive architecture. We started the evaluation with a small survey to probe the appraisal of the notation and infrastructure of AutoPABS. Then we performed a series of tests to measure the gains obtained by applying a population split in an automated A/B testing pipeline, using an extension of the SEAByTE artifact. The survey results show that the participants appraise the usefulness of automating A/B testing pipelines and population split. The test results show that automatically executing pipelines of A/B tests using the self-adaptation architecture with population split accelerates the identification of statistically significant results by exploiting parallel A/B test execution compared to traditional sequential execution of A/B tests.

关键词： Surveys Technological innovation Pipelines Sociology Computer architecture Particle measurements software

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Hybrid Quantum-Classical Computing in Federated Learning With Data Heterogeneity

Hybrid Quantum-Classical Computing in Federated Learning Wit...

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IEEE international symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Keita Hisamori Yi-Han Chiang Hai Lin Yusheng Ji Department of Electrical and Electronic Systems Engineering Osaka Metropolitan University Osaka Japan Information Systems Architecture Science Research Division National Institute of Informatics Tokyo Japan

ISBN: (数字)9798350362244

ISBN: (纸本)9798350362251

Federated learning (FL) has emerged as a promising technique to realize distributed machine learning (ML) in practice. FL enables multiple clients to collaboratively train a common ML model without the need to collect raw data from clients, which therefore has merit in the protection of data privacy. On the other hand, it is known that quantum computing excels in solving specific problems that are computationally prohibitive on classical computers due to its ability to harness quantum superposition and entanglement. However, current noisy intermediate-scale quantum (NISQ) computers have difficulties in dealing with many-qubit computation due to the lack of reliable error-correction schemes, which renders hybrid quantum-classical computing with few qubits a promising alternative. In this paper, we investigate how hybrid quantum-classical computing can be applied to FL while considering the data heterogeneity among clients. To this end, we propose the two-qubit quantum circuit-embedded convolutional neural network (2QCNN) for each client, which incorporates parallel two-qubit variational quantum circuits (VQCs) between the fully connected layers of the CNN. Simulation results show that 2QCNN outperforms the comparison schemes in terms of test accuracies. In addition, the impacts of the number and depth of parallel two-qubit VQCs on the performance of 2QCNN under various degrees of data heterogeneity are further evaluated.

关键词： Computers Quantum computing Accuracy Quantum entanglement Federated learning Simulation Qubit Convolutional neural networks Quantum circuit Protection

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An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing

An Efficient Data Structure for Sparse Bit-Vectors with Appl...

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international symposium on Advanced Research in Asynchronous Circuits and systems

作者： Prafull Purohit Johannes Leugering Rajit Manohar Electrical Engineering Yale University New Haven CT United States Broadband and Broadcast Dept. Fraunhofer Institute for Integrated Circuits (IIS) Erlangen Germany

Iterating over all the elements of a set is a very common problem in highly parallel systems. In hardware, this is typically realized by either storing the set-membership of each element in a fixed-length bit-vector or by storing just the indices of the members in a dynamically sized queue. However, the former solution is only efficient in terms of memory and runtime if each element is a member of the set with approximately 50% probability, whereas the latter is only efficient if the set is extremely sparse. We propose an alternative asynchronous, concurrent, distributed data structure based on a binary tree topology that is more efficient for sets with sparsity in between these two extremes. The proposed structure allows us to construct a set by adding individual elements one at a time in arbitrary order, and to iterate over all these elements exactly once, clearing the set in the process. We analyzed this data structure, simulated its behavior in CHP, synthesized it into an asynchronous digital circuit, optimized the circuits, and performed SPICE simulation to evaluate our design. The results confirm that our proposed structure offers a low-latency, low-power solution for moderately sparse data, and may thus prove useful for asynchronous and neuromorphic systems.

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StencilMART: Predicting Optimization Selection for Stencil Computations across GPUs

StencilMART: Predicting Optimization Selection for Stencil C...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Qingxiao Sun Yi Liu Hailong Yang Zhonghui Jiang Zhongzhi Luan Depei Qian State Key Laboratory of Software Development Environment Beijing China School of Computer Science and Engineering Beihang University Beijing China

Stencil computations are widely used in high performance computing (HPC) applications. Many HPC platforms utilize the high computation capability of GPUs to accelerate stencil computations. In recent years, stencils have become more diverse in terms of stencil order, memory accesses and computation patterns. To adapt diverse stencils to GPUs, a variety of optimization techniques have been proposed such as streaming and retiming. However, due to the diversity of stencil patterns and GPU architectures, no single optimization technique fits all stencils. Besides, it is challenging to choose the most cost-efficient GPU for accelerating target stencils. To address the above problems, we propose StencilMART, an automatic optimization selection framework that predicts the best optimization combination and execution time under a certain parameter setting for stencils on GPUs. Specifically, the StencilMART represents the stencil patterns as binary tensors and neighboring features through tensor assignment and feature extraction. In addition, the StencilMART implements various machine learning methods such as classification and regression that utilize stencil representation and hardware characteristics for execution time prediction. The experiment results show that the StencilMART can achieve accurate optimization selection and performance prediction for various stencils across GPUs.

关键词： distributed processing Tensors High performance computing Graphics processing units Machine learning Computer architecture Feature extraction

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CORtEX 2022 Invited Speaker 3: Neuromorphic computing: from modelling the brain to bio-inspired AI

CORtEX 2022 Invited Speaker 3: Neuromorphic computing: from ...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Oliver Rhodes University of Manchester United Kingdom

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

This talk will introduce the field of neuromorphic computing: researching how to build machines to explore brain function; and using our enhanced understanding of the brain to build better computer hardware and algorithms. Specifically it will discuss spiking neural networks, including how they can be used to model neural circuits, and how these models can be harnessed to develop low-power bio-inspired AI systems.

关键词： Computational modeling Brain modeling Biological system modeling Artificial intelligence Neuromorphic engineering Integrated circuit modeling distributed processing

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[Full] Deep Heuristic for Broadcasting in Arbitrary Networks

[Full] Deep Heuristic for Broadcasting in Arbitrary Networks

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international symposium on parallel and distributed Computing

作者： Hovhannes A. Harutyunyan Narek Hovhannisyan Rakshit Magithiya Department of Computer Science and Software Engineering Concordia University Montreal Canada

ISBN: (数字)9781665488020

ISBN: (纸本)9781665488037

Broadcasting is an information dissemination problem in a connected graph in which one vertex, called the originator, must distribute a message to all other vertices by placing a series of calls along the edges of the graph. Every time the informed vertices aid the originator in distributing the message. Finding the broadcast time of any vertex in an arbitrary graph is NP-complete. We designed an efficient heuristic, which improves the results of existing heuristics in most cases. Extensive simulations show that our new heuristic outperforms the existing ones for most of the commonly used interconnection networks in some network models generated by network simulator ns-2.

关键词： Multiprocessor interconnection Computational modeling Broadcasting distributed computing

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