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Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation 33

Improving Phased Transactional Memory via Commit Throughput ...

引用

33rd IEEE international symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Morales, Catalina Munoz Honorio, Bruno Baldassin, Alexandro Araujo, Guido Univ Estadual Campinas Inst Comp Campinas Brazil Univ Estadual Paulista UNESP Sao Paulo Brazil

ISBN: (纸本)9781665443012

Transactional Memory (TM) is a programming abstraction that aims to ease parallel programming in shared-memory architectures. Both Hardware (HTM) and software Transactional Memory (STM) implementations have been extensively studied in the literature. Modern approaches seek to combine both HTM and STM to better exploit performance. In particular, Phased TMs (PhTMs) systems execute transactions in phases, not allowing both hardware and software transactions to run concurrently to avoid coordination overheads. The main challenge in designing PhTM systems is to dynamically choose a proper execution mode. Usually, a transition mechanism is developed based on metrics such as transaction size and abort rates to guide the phase migration. However, the tuning of such metrics is not an easy task, since it may lead to over-fitting and poor performance for the general case. This paper advances state-of-the-art research on PhTM by proposing a different approach to phase selection: the use of commit throughput and cache simulation to mimic the behavior of HTM storage constraints while in STM mode. When compared to previous work, this approach leads to a simpler and more efficient mechanism to assess the state of the execution modes in run time. Experimental results using STAMP and two graph processing applications show how the Commit Throughput-based mechanism is able to outperform a state-of-the-art Phased TM runtime (PhTM*) with speedups of up to 5x.

关键词： Hardware Transactional Memory software Transactional Memory shared memory

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TEE-based decentralized recommender systems: The raw data sharing redemption

TEE-based decentralized recommender systems: The raw data sh...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Akash Dhasade Nevena Dresevic Anne-Marie Kermarrec Rafael Pires EPFL - Swiss Federal Institute of Technology Lausanne Switzerland

Recommenders are central in many applications today. The most effective recommendation schemes, such as those based on collaborative filtering (CF), exploit similarities between user profiles to make recommendations, but potentially expose private data. Federated learning and decentralized learning systems address this by letting the data stay on user's machines to preserve privacy: each user performs the training on local data and only the model parameters are shared. However, sharing the model parameters across the network may still yield privacy breaches. In this paper, we present Rex, the first enclave-based decentralized CF recommender. Rex exploits Trusted execution environments (TEE), such as Intel software guard extensions (SGX), that provide shielded environments within the processor to improve convergence while preserving privacy. Firstly, Rex enables raw data sharing, which ultimately speeds up convergence and reduces the network load. Secondly, Rex fully preserves privacy. We analyze the impact of raw data sharing in both deep neural network (DNN) and matrix factorization (MF) recommenders and showcase the benefits of trusted environments in a full-fledged implementation of Rex. Our experimental results demonstrate that through raw data sharing, Rex significantly decreases the training time by 18.3 x and the network load by 2 orders of magnitude over standard decentralized approaches that share only parameters, while fully protecting privacy by leveraging trustworthy hardware enclaves with very little overhead.

关键词： Training Data privacy Neural networks Telecommunication traffic Collaborative work Privacy breach software

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A software-Scalable Analog-to-Digital Converter for Particle Detectors in 28nm bulk CMOS

A Software-Scalable Analog-to-Digital Converter for Particle...

引用

IEEE symposium on Nuclear Science (NSS/MIC)

作者： L. Krystofiak V. Christ S. Kusuma C. Grewing A. Zambanini S. van Waasen Juelich Research Center Central Institute of Engineering Electronics and Analytics ZEA-2 – Electronic Systems Juelich North Rhine-Westphalia Germany Faculty of Engineering – Communication Systems University of Duisburg-Essen Duisburg North Rhine-Westphalia Germany

New discoveries in particle physics put an ever-increasing demand on the installed electronics in detector experiments. Currently used process technologies for integrated electronics, as 65nm and larger, are reaching their limits of resolution over power consumption and integration factor. The consequential progression to a smaller process technology comes with increased cost and design complexity resulting in a higher impact on the overall success of a project. The currently discussed way out of this predicament is concentrating cost and effort in fewer, more generic solutions covering a wider range of applications. A first prototype of a software-scalable Analog-to-Digital converter manufactured in a 28nm bulk CMOS process technology is presented, which is part of a generic frontend solution concept. It incorporates a low-power mode with 8 bit of resolution, a maximum sample rate of 480 MSPS, and a power consumption of 1.62 mW. When higher resolution is needed, a high-precision mode can be used with a resolution of 11 bit, a maximum sample rate of 350 MSPS and a power consumption of 5.6 mW. The complete software-scalable Analog-to-Digital converter takes 0.029 mm² of chip area. Overall, the first chip is 1 mm² in size. It includes two channels, a high-speed parallel communication interface, a clock buffer and memory for 8168 Analog-to-Digital converter samples.

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IoT and Computer Vision Based Aquaponics System

IoT and Computer Vision Based Aquaponics System

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ACIS international Conference on software engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： Nazib Ahmad Md. Mehedi Hasan Mhamudur Rohomun Raihana Irin Rashedur M. Rahman Department of Electrical and Computer Engineering North South University Dhaka-1229 Bangladesh

A farming method known as aquaponics aims to be a more effective response to the world's worries about food production and scarcity. In order to produce plants or vegetables in addition to fish to meet the rising global demand for food, this technique combines aquaculture (fish farming) and aquaponics (plants grown without soil). This technique or system promises to utilize less water, fertilizer, pesticides, and space while yet producing as much as conventional farming. The challenge is making it more usable and scalable for commercial and public use. To overcome such challenges, this technique must be intelligent and automated by rigorous sensing, monitoring, and system control. Our current research aims to develop a practical smart IoT-based aquaponics system. It offers a workable solution and ideas for further investigation while also looking for gaps in the earlier investigations.

关键词： Temperature sensors Temperature measurement Production Soil Fish Control systems Sensors

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SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a single Datacenter FPGA Card

SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a s...

引用

IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Riadh Ben Abdelhamid Vladislav Valek Dirk Koch Department of Engineering Heidelberg University Heidelberg Germany

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

SPARKLE is a many-core multi-threaded RISC-V architecture designed for scalable parallel processing. Our implementation on a Xilinx VU9P datacenter-class FPGA comprises 1,024 cores, and 16,384 Harts (Hardware threads), clocking at 400MHz and spanning the entirety of the chip, including a PCIe backplane. As such, SPARKLE delivers 400 GIPS (Giga Instructions Per Second), demonstrating the feasibility of large-scale high-speed parallelism. SPARKLE is very flexible and allows users to define different configurations for memory, instruction set extensions, and cluster organizations. For instance, a smaller-footprint 56-core (896-Hart) cluster can operate at 500 MHz, on the same *** the heart of SPARKLE, its core, code-named BRISKI (Barrel RISC-V for Kilo-core Implementations) is among the fastest existing on literature and can operate at 650+ MHz. BRISKI is a highly-optimized barrel processor core that implements the full user-mode RV32I, as well as RV32A LR.W/SC.W subset and CSRRS instruction for Hart ID retrieval.

关键词： Power demand Instruction sets Scalability Standards organizations Computer architecture Organizations parallel processing software Synchronization Field programmable gate arrays

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ScaMP: Scalable Meta-parallelism for Deep Learning Search

ScaMP: Scalable Meta-Parallelism for Deep Learning Search

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： Quentin Anthony Lang Xu Aamir Shafi Hari Subramoni Dhabaleswar K. DK Panda Department of Computer Science and Engineering The Ohio State University

Deep Learning (DL) models are growing exponentially and require increasingly powerful High Performance Computing (HPC) systems to train them. Achieving state-of-the-art results requires carefully tuning the DL model architecture and training settings, which is a time-consuming process commonly relegated to distributed search frameworks and trial-and-error. However, search frameworks don't provide a flexible parallelism scheme within and among the chosen DL framework for modern out-of-core DL models. In this paper, we propose Scalable Meta-parallelism for Deep Learning Search (ScaMP): a distributed Hyperparameter Optimization (HPO) and Neural Architecture Search (NAS) framework that supports out-of-core models with flexible parallelism schemes. SCaMP is integrated into the modern DL ecosystem, and enables both efficient parallel training of concurrent candidate architectures and aggregate device memory saturation via a powerful load balancing engine. SCaMP estimates the memory requirements of each candidate architecture and automatically applies the appropriate model-parallel degree and maximum batch size supported for the given candidate. Further, HPO and NAS with SCaMP are highly customizable via flexible configuration options. We evaluate the benefits of our designs on synthetic training benchmarks and in training a state-of-the-art vision transformer model. We select transformers as a candidate DL model type and demonstrate a 29% improvement in end-to-end HPO time on 32 V100 GPUs on the Lassen and ThetaGPU HPC systems. Further, we demonstrate a reduction in the proportion of NAS time spent in communication from 28% to 15%. Finally, we thoroughly verify the correctness of SCaMP by training a state-of-the-art SwinIR model.

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ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support

ReconOS64: A Hardware Operating System for Modern Platform F...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Lennart Clausing Marco Platzner Department of Computer Science Paderborn University Paderborn Germany

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Reconfigurable hardware operating systems provide software-like abstractions for hardware accelerators. In particu-lar abstractions that view hardware accelerators as threads and integrate them into a multi-threaded environment have received popularity. However, such abstractions are not yet available for latest platform FPGAs. In this paper, we present ReconOS 64 , a reconfigurable hard-ware operating system for 64-Bit modern platform FPGAs. We discuss the architecture and the build flow and report on a number of experiments that evaluate the performance of the system. In particular, we compare the performance to a previous, 32- Bit ReconOS system. The evaluation shows that the step towards 64- Bit is not only necessary to make hardware operating system support available for modern platform FPGAs, but also improves the performance of operating system calls and memory accesses for hardware threads.

关键词： distributed processing Operating systems Instruction sets Conferences Data transfer Resource management Field programmable gate arrays

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How Far Have We Come in Detecting Anomalies in distributed systems? An Empirical Study with a Statement-level Fault Injection Method 31

How Far Have We Come in Detecting Anomalies in Distributed S...

引用

IEEE 31st international symposium on software Reliability engineering (ISSRE)

作者： Yang, Yong Wu, Yifan Pattabiraman, Karthik Wang, Long Li, Ying Peking Univ Sch Software & Microelect Beijing Peoples R China Univ British Columbia Vancouver BC Canada IBM TJ Watson Res Ossining NY 10562 USA Peking Univ Natl Engn Ctr Software Engn Beijing Peoples R China

ISBN: (纸本)9781728198705

Anomaly detection in distributed systems has been a fertile research area, and a range of anomaly detectors have been proposed for distributed systems. Unfortunately, there is no systematic quantitative study of the efficacy of different anomaly detectors, which is of great importance to reveal the deficiencies of existing anomaly detectors and shed light on future research directions. In this paper, we investigate how various anomaly detectors behave on anomalies of different types and the reasons for the same, by extensively injecting software faults into three widely-used distributed systems. We use a statement-level fault injection method to observe the anomalies, characterize these anomalies, and analyze the detection results from anomaly detectors of three categories. We find that: (1) the distributed systems' own error reporting mechanisms are able to report most of the anomalies (from 82.1% to 92.8%) but they incur a high false alarm rate of 26.6%. (2) State-of-the-art anomaly detectors are able to detect the existence of anomalies with 99.08% precision and 90.60% recall, but there is still a long way to go to pinpoint the accurate location of the detected anomalies, and (3) Log-based anomaly detection techniques outperform other anomaly detection techniques, but not for all anomaly types.

关键词： anomaly detection distributed systems fault injection dependability

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A Scalable parallel Partition Tridiagonal Solver for Many-Core and Low B/F Processors

A Scalable Parallel Partition Tridiagonal Solver for Many-Co...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Tatsuya Mitsuda Kenji Ono Graduate School and Faculty of Information Science and Electrical Engineering Kyushu University Fukuoka Japan Research Institute for Information and Technology Kyushu University Fukuoka Japan

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Tridiagonal systems are among the most fundamental computations in science, engineering, and mathematics, and one solver used in such systems is Tree Partitioning Reduction (TPR), which is a divide-and-conquer method that solves large-scale linear equations by dividing them and then computing the parts in parallel within different local memory threads. Herein, we propose an improved TPR algorithm that has a parallel cyclic reduction flavor, with which we reduced the number of algorithm steps by approximately half while simultaneously increasing arithmetic intensity and cache reusability. A performance evaluation conducted on an Intel Skylake-SP microprocessor showed a high hit ratio for the L1 cache and that our solver was as much as 31 times faster on 32 threads for 262144 equations. In the case of a Nvidia Tesla P100 GPU, our method processed 10 MRow/s more than TPR and cuSPARSE.

关键词： Performance evaluation Microprocessors Scalability Instruction sets Memory management Graphics processing units Approximation algorithms

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Nexus: Efficient and Conflict-Equivalent DAG-Based Permissioned Blockchain Sharding

Nexus: Efficient and Conflict-Equivalent DAG-Based Permissio...

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international Workshop on Quality of Service

作者： Yuchao Zhang Xiaotian Wang Xiaofeng He School of Computer Science (National Pilot Software Engineering School) Beijing University of Posts and Telecommunications Beijing China

ISBN: (数字)9798350350128

ISBN: (纸本)9798350350135

Sharding is one of the most promising solutions to tackle the well-known scalability issue in blockchain by dividing the network into multiple parallel committees. However, inefficient and insecure handling of cross-shard transactions can lead to a decline in the system service quality. Existing permissioned blockchains are mainly based on the classic two-phase commit (2PC) and two-phase locking (2PL) from traditional distributed databases to implement cross-shard transactions with deterministic safety, but this also leads to issues such as decreased system throughput and frequent transaction aborts. In this paper, we introduce Nexus, an efficient and conflict-equivalent sharded permissioned blockchains to overcome the aforementioned challenges. The core idea of Nexus is to construct a directed acyclic graph (DAG) among all shards to establish a partial order of blocks, while leaving transaction dissemination and final ordering to be completed in parallel by each shard. Nexus alleviate the overhead of global ordering through a efficient consensus process, and ensure that all transactions with overlapping read and write sets can be committed in the same relative order across different shards. A prototype of Nexus is implemented and evaluated, and experimental results show that Nexus achieves approximately 70% and 50% throughput improvement over AHL and SharPer under default settings.

关键词： Sharding Directed acyclic graph Protocols Scalability Prototypes Quality of service Throughput

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