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检索条件"任意字段=Numerical Validation in Current Hardware Architectures 2008"
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numerical validation in current hardware architectures 2008
Numerical Validation in Current Hardware Architectures 2008
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numerical validation in current hardware architectures 2008
The proceedings contain 22 papers. The topics discussed include: a modified staggered correction arithmetic with enhanced accuracy and very wide exponent range;a note on some applications of interval arithmetic in hie...
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08021 Abstracts Collection numerical validation in current hardware architectures
08021 Abstracts Collection Numerical Validation in Current H...
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numerical validation in current hardware architectures 2008
作者: Luther, Wolfram Cuyt, Annie Krämer, Walter Markstein, Peter Univ. Duisburg-Essen Germany U Antwerp BE Belgium BU Wuppertal Germany HP Labs Palo Alto United States
From 06.01. to 11.01.2008, the Dagstuhl Seminar 08021 "numerical validation in current hardware architectures" was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During th... 详细信息
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Summary of the seminar 08021 numerical validation in current hardware architectures - From embedded system to high-end computational grids
Summary of the seminar 08021 Numerical validation in current...
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numerical validation in current hardware architectures 2008
作者: Cuyt, Annie Krämer, Walter Luther, Wolfram Markstein, Peter University of Antwerp Belgium University of Wuppertal Germany University of Duisburg-Essen Germany Woodside California United States
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numerical validation in current hardware architectures  1
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丛书名: Lecture Notes in Computer Science
1000年
作者: Annie Cuyt Walter Krämer Wolfram Luther Peter Markstein
This book constitutes the thoroughly refereed post-proceedings of the Dagstuhl Seminar 08021 on numerical validation in current hardware architectures held at Dagstuhl Castle, Germany, in January 2008. The 16 revised ... 详细信息
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numerical validation in current hardware architectures  2009
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丛书名: Lecture Notes in Computer Science
2009年
作者: Annie A.M. Cuyt Walter Krämer Wolfram Luther Peter Markstein
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numerical validation in current hardware architectures - International Dagstuhl Seminar, Revised Papers
Numerical Validation in Current Hardware Architectures - Int...
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International Dagstuhl Seminar on numerical validation in current hardware architectures
The proceedings contain 15 papers. The topics discussed include: discussions on an interval arithmetic standard at Dagstuhl seminar;continued fractions for special functions: handbook and software;a modified staggered...
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Robustness of Boolean Operations on Subdivision-Surface Models
Robustness of Boolean Operations on Subdivision-Surface Mode...
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International Dagstuhl Seminar on numerical validation in current hardware architectures
作者: Jiang, Di Stewart, Neil F. Univ Montreal Dept IRO Montreal PQ H3C 3J7 Canada
This paper describes an algorithm to perform Boolean operations, based on the use of limit meshes, in the case when input objects are defined in terms of triangular meshes and Loop subdivision. The focus of the paper ... 详细信息
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numerical Verification Assessment in Computational Biomechanics
Numerical Verification Assessment in Computational Biomechan...
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International Dagstuhl Seminar on numerical validation in current hardware architectures
作者: Auer, Ekaterina Luther, Wolfram Univ Duisburg Essen Dept Comp Sci & Appl Cognit Sci Essen Germany
In this paper, we present several aspects of the recent project PROREOP developing a new prognosis system for optimizing patient-specific preoperative surgical planning for the human skeletal system. We address verifi... 详细信息
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A Modified Staggered Correction Arithmetic with Enhanced Accuracy and Very Wide Exponent Range
A Modified Staggered Correction Arithmetic with Enhanced Acc...
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International Dagstuhl Seminar on numerical validation in current hardware architectures
作者: Blomquist, Frithjof Hofschuster, Werner Kraemer, Walter Berg Univ Wuppertal D-42097 Wuppertal Germany
A so called staggered precision arithmetic is a special kind of a multiple precision arithmetic based on the underlying floating point data format (typically IEEE double format) and fast floating point operations as w... 详细信息
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Modular Hybrid Transformers Toward Grid Resilience: Efficiency Analysis and Operation
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2024年 第9期71卷 10086-10097页
作者: Prabowo, Yos Iyer, Vishnu Mahadeva Agarwal, Apoorv Bhattacharya, Subhashish Aeloiza, Eddy North Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27697 USA Indian Inst Sci Dept Elect Engn Bengaluru 560012 India ABB US Corp Res Raleigh NC 27606 USA
This article proposes modular hybrid transformer architectures to improve grid resilience. The conventional line-frequency transformer is augmented with a partially rated power electronics converter to realize a hybri... 详细信息
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