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检索条件"任意字段=PDSE 2000: International Symposium on Software Engineering for Parallel and Distributed Systems"

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Design and Implementation of a Large Scale Tree-Based QR Decomposition Using a 3D Virtual Systolic Array and a Lightweight Runtime

Design and Implementation of a Large Scale Tree-Based QR Dec...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Ichitaro Yamazaki Jakub Kurzak Piotr Luszczek Jack Dongarra University of Tennessee Knoxville TN USA University of Manchester Manchester UK Oak Ridge National Laboratory Oak Ridge TN USA

ISBN: (纸本)9781479941155

A systolic array provides an alternative computing paradigm to the von Neuman architecture. Though its hardware implementation has failed as a paradigm to design integrated circuits in the past, we are now discovering that the systolic array as a software virtualization layer can lead to an extremely scalable execution paradigm. To demonstrate this scalability, in this paper, we design and implement a 3D virtual systolic array to compute a tile QR decomposition of a tall-and-skinny dense matrix. Our implementation is based on a state-of-the-art algorithm that factorizes a panel based on a tree-reduction. Using a runtime developed as a part of the parallel Ultra Light Systolic Array Runtime (PULSAR) project, we demonstrate on a Cray-XT5 machine how our virtual systolic array can be mapped to a large-scale machine and obtain excellent parallel performance. This is an important contribution since such a QR decomposition is used, for example, to compute a least squares solution of an overdetermined system, which arises in many scientific and engineering problems.

关键词： Arrays Runtime Message systems software Three-dimensional displays Computers Hardware

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Efficient Multicast Algorithms for Mesh and Torus Networks

Efficient Multicast Algorithms for Mesh and Torus Networks

引用

international symposium on parallel and distributed Processing with Applications, ISPA

作者： Hovhannes A. Harutyunyan Ankit Malani Department of Computer Science and Software Engineering Concordia University Montreal QC Canada

With the increasing popularity of multicomputers, efficient way of communication within its processors is a popular area of research. Multicomputers refer to a computer system that has multiple processors, they have high computational power and they can perform multiple tasks concurrently. Mesh and Torus are some of the commonly used network topologies in building multicomputer systems. Their performance highly depends on the underlying network communication such as multicast. Multicast is a communication method in which a message is sent from a source node to a certain number of destinations. Two major parameters used to evaluate multicast are time that a multicast process takes to deliver the message to all destinations and traffic that indicates the number of links used for this process. Research indicates that in general, it is NP-complete to find an optimal multicasting algorithm which is efficient on both time and traffic. This paper suggests two new algorithms to achieve multicast in mesh and torus networks. Extensive simulations of these algorithms show that in practice they perform better than existing ones.

关键词： Algorithm design and analysis Program processors Multicast communication Routing Mesh networks Computers Unicast

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POD: Performance Oriented I/O Deduplication for Primary Storage systems in the Cloud

POD: Performance Oriented I/O Deduplication for Primary Stor...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Bo Mao Hong Jiang Suzhen Wu Lei Tian Software School of Xiamen University China Department of Computer Science and Engineering University of Nebraska-Lincoln USA Department of Xiamen University Computer Science China

ISBN: (纸本)9781479938018

Recent studies have shown that moderate to high data redundancy clearly exists in primary storage systems in the Cloud. Our experimental studies reveal that data redundancy exhibits a much higher level of intensity on the I/O path than that on disks due to the relatively high temporal access locality associated with small I/O requests to redundant data. On the other hand, we also observe that directly applying data deduplication to primary storage systems in the Cloud will likely cause space contention in memory and data fragmentation on disks. Based on these observations, we propose a Performance-Oriented I/O Deduplication approach, called POD, rather than a capacity-oriented I/O deduplication approach, represented by iDedup, to improve the I/O performance of primary storage systems in the Cloud without sacrificing capacity savings of the latter. The salient feature of POD is its focus on not only the capacity-sensitive large writes and files, as in iDedup, but also the performance-sensitive while capacity-insensitive small writes and files. The experiments conducted on our lightweight prototype implementation of POD show that POD significantly outperforms iDedup in the I/O performance measure by up to 87.9% with an average of 58.8%. Moreover, our evaluation results also show that POD achieves comparable or better capacity savings than iDedup.

关键词： Indexes Redundancy Educational institutions Memory management Prototypes Cache storage Monitoring

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Remote Invalidation: Optimizing the Critical Path of Memory Transactions

Remote Invalidation: Optimizing the Critical Path of Memory ...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Ahmed Hassan Roberto Palmieri Binoy Ravindran Electrical and Computer Engineering Department Virginia Tech Blacksburg Virginia USA

software Transactional Memory (STM) systems are increasingly emerging as a promising alternative to traditional locking algorithms for implementing generic concurrent applications. To achieve generality, STM systems incur overheads to the normal sequential execution path, including those due to spin locking, validation (or invalidation), and commit/abort routines. We propose a new STM algorithm called Remote Invalidation (or RInval) that reduces these overheads and improves STM performance. RInval's main idea is to execute commit and invalidation routines on remote server threads that run on dedicated cores, and use cache-aligned communication between application's transactional threads and the server routines. By remote execution of commit and invalidation routines and cache-aligned communication, RInval reduces the overhead of spin locking and cache misses on shared locks. By running commit and invalidation on separate cores, they become independent of each other, increasing commit concurrency. We implemented RInval in the Rochester STM framework. Our experimental studies on micro-benchmarks and the STAMP benchmark reveal that RInval outperforms InvalSTM, the corresponding non-remote invalidation algorithm, by as much as an order of magnitude. Additionally, RInval obtains competitive performance to validation-based STM algorithms such as NOrec, yielding up to 2x performance improvement.

关键词： Servers Synchronization Benchmark testing Instruction sets Concurrent computing Scalability Hardware

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PLDSRC: A Multi-threaded Compressor/Decompressor for Massive DNA Sequencing Data

PLDSRC: A Multi-threaded Compressor/Decompressor for Massive...

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The 13th international symposium on distributed Computing and Applications to Business,engineering and Science(DCABES 2014)(第十三届分布式计算及其应用国际学术研讨会)

作者： Ke Zhan Chao Yang Changyou Zhang Jingjing Zheng Ting Wang Institute of Software Chinese Academy of SciencesBeijing 100190China University of Chinese Academy Institute of Software Chinese Academy of SciencesBeijing 100190China State Key Laboratory of Compu Institute of Software Chinese Academy of SciencesBeijing 100190China

ISBN: (纸本)9781479941681

To face the rapid growth of DNA sequencing data,it is of great importance to study high efficiency compression techniques to reduce the cost of storing the massive amount of sequencing *** this paper,we propose a parallel DNA data compressor/decompressor,PLDSRC,based on the famous serial DSRC *** first analyze the compression and decompression algorithm in DSRC and identity three basic operations,namely read,work,and *** a single pipeline parallel algorithm is proposed to accelerate the compression/decompression *** further exploit today’s popular multi-core,multi-socket systems based on the non-uniform memory access (NUMA) architecture,we extend the single pipeline approach to the multi-pipeline *** on two different platforms are done and show that PLDSRC in both single and multiple pipeline forms is able to speed up DNA sequencing data compression/decompression greatly,while maintaining the same compressing *** indicate that the maximum speedup of PLDSRC on compressing and decompressing is respectively around 24.71x and 22.00x,as compared to the serial DSRC software.

关键词： DNA sequencing compression DSRC PLDSRC Multi-pipeline NUMA

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F-SEFI: A Fine-Grained Soft Error Fault Injection Tool for Profiling Application Vulnerability

F-SEFI: A Fine-Grained Soft Error Fault Injection Tool for P...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Qiang Guan Nathan Debardeleben Sean Blanchard Song Fu Ultrascale Systems Research Center Los Alamos National Laboratory Department of Computer Science and Engineering University of North Texas

ISBN: (纸本)9781479938018

As the high performance computing (HPC) community continues to push towards exascale computing, resilience remains a serious challenge. With the expected decrease of both feature size and operating voltage, we expect a significant increase in hardware soft errors. HPC applications of today are only affected by soft errors to a small degree but we expect that this will become a more serious issue as HPC systems grow. We propose F-SEFI, a Fine-grained Soft Error Fault Injector, as a tool for profiling software robustness against soft errors. In this paper we utilize soft error injection to mimic the impact of errors on logic circuit behavior. Leveraging the open source virtual machine hypervisor QEMU, F-SEFI enables users to modify emulated machine instructions to introduce soft errors. F-SEFI can control what application, which sub-function, when and how to inject soft errors with different granularities, without interference to other applications that share the same environment. F-SEFI does this without requiring revisions to the application source code, compilers or operating systems. We discuss the design constraints for F-SEFI and the specifics of our implementation. We demonstrate use cases of F-SEFI on several benchmark applications to show how data corruption can propagate to incorrect results.

关键词： Hardware Benchmark testing Virtual machine monitors Probes Registers Virtual machining Circuit faults

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An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition

An FPGA Implementation of the Hestenes-Jacobi Algorithm for ...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Xinying Wang Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Ames Iowa USA

ISBN: (纸本)9781479941155

As a useful tool for dimensionality reduction, Singular Value Decomposition (SVD) plays an increasingly significant role in many scientific and engineering applications. The high computational complexity of SVD poses challenges for efficient signal processing and data analysis systems, especially for time sensitive applications with large data sets. While the emergence of FPGAs provides a flexible and low-cost opportunity to pursue high-performance SVD designs, the classical two-sided Jacobi rotation-based SVD architectures are restricted in terms of scalability and input matrix representation. The Hestenes-Jacobi algorithm offers a more parallelizable solution to analyze arbitrary rectangular matrices, however, to date both FPGA and GPU-based implementations have not lived up to the algorithm's potential. In this paper, we introduce a floating-point Hestenes-Jacobi architecture for SVD, which is capable of analyzing arbitrary sized matrices. Our implementation on an FPGA-based hybrid acceleration system demonstrates improved efficiency of our architecture compared to an optimized software-based SVD solution for matrices with small to medium column dimensions, even with comparably large row dimensions. The dimensional speedups can be achieved range from 3.8x to 43.6x for matrices with column dimensions from 128 to 256 and row sizes from 128 to 2048. Additionally, we also evaluate the accuracy of our SVD process through convergence analysis.

关键词： Jacobian matrices Vectors Computer architecture Matrix decomposition Field programmable gate arrays Covariance matrices Algorithm design and analysis

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Cross Resource Optimisation of Database Functionality across Heterogeneous Processors

Cross Resource Optimisation of Database Functionality across...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Eoghan O'Neill John McGlone J.G.F Coutinho Andrew Doole Carmelo Ragusa O. Pell P. Sanders SAP HANA Cloud Comput. Syst. Eng. UK Systems Engineering SAP HANA Cloud Computing Belfast UK Imperial College London UK Maxeler Technologies UK

Significant application performance improvements can be achieved by heterogeneous compute technologies, such as multi-core CPUs, GPUs and FPGAs. The HARNESS project is developing architectural principles that enable the next generation cloud platforms to incorporate such devices thereby vastly increasing performance, reducing energy consumption, and lowering associated cost profiles. Along with management and integration of such devices in a cloud environment, a key issue is enabling enterprise-level software to make effective use of such compute devices. A major obstacle in adopting heterogeneous compute resources is the requirement that at design time the developer must decide on which device to execute portions of the application. For an interactive application, such as SAP HANA where there are many on-going tasks and processes, this type of decision is impossible to predict at design time. What is required is the ability to decide, at run-time, the optimal compute device to execute a task. This paper extends upon existing work on SHEPARD to support non-OpenCL devices. SHEPARD decouples application development from the target platform and enables the required run-time allocation of tasks to heterogeneous computing devices. This paper establishes SHEPARD's capability to: (1) select the appropriate compute device to execute tasks, (2) dynamically load the device application code at runtime, and (3) execute the application logic. Experiments demonstrate how SHEPARD optimises the execution of a SAP HANA database management function across heterogeneous compute devices and perform automatic run-time task allocation.

关键词： Runtime Performance evaluation Resource management Field programmable gate arrays Databases Dictionaries Kernel

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PLDSRC: A Multi-threaded Compressor/Decompressor for Massive DNA Sequencing Data

PLDSRC: A Multi-threaded Compressor/Decompressor for Massive...

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13th international symposium on distributed Computing and Applications to Business,engineering & Science（DCABES 2014）

作者： Ke Zhan Chao Yang Changyou Zhang Jingjing Zheng Ting Wang Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences State Key Laboratory of Computer Science Chinese Academy of Sciences

To face the rapid growth of DNA sequencing data, it is of great importance to study high efficiency compression techniques to reduce the cost of storing the massive amount of sequencing data. In this paper, we propose a parallel DNA data compressor/decompressor, PLDSRC, based on the famous serial DSRC software. We first analyze the compression and decompression algorithm in DSRC and identity three basic operations, namely read,work, and write. Then a single pipeline parallel algorithm is proposed to accelerate the compression/decompression procedure. To further exploit today's popular multi-core,multi-socket systems based on the non-uniform memory access(NUMA) architecture, we extend the single pipeline approach to the multi-pipeline case. Experiments on two different platforms are done and show that PLDSRC in both single and multiple pipeline forms is able to speed up DNA sequencing data compression/decompression greatly, while maintaining the same compressing ratio. Examples indicate that the maximum speedup of PLDSRC on compressing and decompressing is respectively around 24.71 x and 22.00 x, as compared to the serial DSRC software.

关键词： DNA sequencing compression DSRC PLDSRC Multi-pipeline NUMA

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An Improved KM Algorithm for Computing Structural Index of DAE System

An Improved KM Algorithm for Computing Structural Index of D...

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12th international symposium on distributed Computing and Applications to Business, engineering and Science (DCABES)

作者： Zeng, Yan Wu, Xuesong Cao, Jianwen Chinese Acad Sci Inst Software Lab Parallel Software & Computat Sci Software Beijing 100190 Peoples R China

ISBN: (纸本)9780769550602

This paper proposes an improved KM algorithm to computing the structural index of linear time-invariant Differential Algebraic Equation (DAE) systems. The problem is of practical significance in index reduction based on structural index of DAE system and combinatorial relaxation theory. This improved KM algorithm combines greedy idea and classical KM algorithm. It first computes matches as much as possible using greedy technology, and then call KM algorithm to search the matches for the unmatched vertices during the step of greedy technology. The improved KM algorithm reduces the running time bound by a factor of r, the number of matches searched using greedy algorithm. Generally, the time complexity is O(r(2) + (n - r)n(2)), the optimal time is O(n(2)).

关键词： DAE Index Reduction Structural Index Bipartite Graph Greedy KM Algorithm

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