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共 944 条记录，以下是181-190 订阅

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On adaptive contention management strategies for software transactional memory

On adaptive contention management strategies for software tr...

引用

2012 10th IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2012

作者： Yu, Xiao He, Zhengyu Hong, Bo School of Electrical and Computer Engineering Georgia Institute of Technology United States

ISBN: (纸本)9780769547015

software Transaction Memory (STM) is an alternative synchronization method to the traditional lock-based schemes. In an STM system, the contention manager(CM) decides what action to take when a conflict occurs. CM is crucial to the performance of STM systems. However, the performance of existing CMs is sensitive to the transaction workloads and STM configurations. A static policy is therefore unsatisfactory. In this paper, we argue that adaptive contention manager (ACM) is necessary and feasible. We further present an ACM policy that can adaptively choose a suitable CM during run-time. We prove that our adaptation strategy preserves live-lock (starvation) freedom as long as the pool of CMs to adapt from contains at least one live-lock free (starvation free) CM. Experimental results demonstrate that our approach can choose proper CMs and achieves higher average throughput than existing static CM strategies. © 2012 IEEE.

关键词： Managers

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Performance modeling of design patterns for distributed computation

Performance modeling of design patterns for distributed comp...

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2012 IEEE 20th international symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems, MASCOTS 2012

作者： Strebelow, Ronald Tribastone, Mirco Prehofer, Christian Fraunhofer Institute for Communication Systems ESK Munich Germany Department for Informatics Ludwig-Maximilians-Universität Munich Germany

ISBN: (纸本)9780769547930

In software engineering, design patterns are commonly used and represent robust solution templates to frequently occurring problems in software design and implementation. In this paper, we consider performance simulation for two design patterns for processing of parallel messaging. We develop continuous-time Markov chain models of two commonly used design patterns, Half-Sync/Half-Async and Leader/Followers, for their performance evaluation in multicore machines. We propose a unified modeling approach which contemplates a detailed description of the application-level logic and abstracts away from operating system calls and complex locking and networking application programming interfaces. By means of a validation study against implementations on a 16-core machine, we show that the models accurately predict peak throughputs and variation trends with increasing concurrency levels for a wide range of message processing workloads. We also discuss the limits of our models when memory-level internal contention is not captured. © 2012 IEEE.

关键词： Application programming interfaces (API)

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Efficient On-line Hardware/software Task Scheduling for Dynamic Run-time Reconfigurable systems

Efficient On-line Hardware/Software Task Scheduling for Dyna...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Ahmed Al-Wattar Shawki Areibi Faycal Saffih University of Guelph Guelph ON CA School of Engineering University of Guelph Guelph Canada

Modern reconfigurable devices such as FPGAs can be reconfigured at run time. Some of them can be dynamically partially reconfigured, which means part of the FPGA is changed without interrupting other parts. This feature adds tremendous flexibility to the Reconfigurable Computing (RC) Field but also introduces challenges. Reconfigurable Operating systems tend to ease applications development and most importantly applications verifications and maintenance. In this paper we propose novel scheduling algorithms for reconfigurable computing that can handle both hardware and software tasks. The algorithms proposed reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software/hardware, and give priority to hardware tasks. Results obtained indicate that adding a software processor element not only adds flexibility, but also increases system performance. Two on-line schedulers were designed and implemented. RCSched-I is a simple based implementation that nominates the first available free Partial Reconfigurable Region (PRR) for new tasks. RCSched-II on the other hand nominates any free PRR. Both schedulers check the nominated PRR(s) against the ready task for a match, then decide if there is a need for reconfiguration or not. RCSched-II reconfigures the least recently configured PRR, which increases hardware tasks reuse and decreases total processing time.

关键词： Hardware software Field programmable gate arrays Schedules Dynamic scheduling Scheduling algorithms software algorithms

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Teaching by Example: Using Analogies and Live Coding Demonstrations to Teach parallel Computing Concepts to Undergraduate Students

Teaching by Example: Using Analogies and Live Coding Demonst...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Nasser Giacaman Department of Electrical and Computer Engineering University of Auckland Auckland New Zealand

ISBN: (纸本)9781467309745

This paper details recent experience in teaching parallel computing concepts to undergraduate Computer Science students. By taking a practical approach in delivering the material, students are shown to have grasped essential multi-threading concepts in Java, ensuring they are able to implement the necessary skills themselves. The motivation for parallel computing is clearly demonstrated early in the course, to immediately convince students of the importance in developing their parallel computing skills, should they wish to be effective software developers. Within only 4 weeks, students are able to correctly and efficiently multi-thread a sequential desktop application (with a Graphical User Interface) that is both responsive (does not freeze the user interface) and perform ant (utilises the underlying multi-core processor). The student evaluations confirm that using live coding demonstrations and analogies were most helpful in learning parallel computing.

关键词： parallel processing Message systems Concurrent computing Java Education Encoding

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Simulation and Support of Critical Activities by Mobile Agents in Pervasive and Ubiquitous Scenarios

Simulation and Support of Critical Activities by Mobile Agen...

引用

international symposium on parallel and distributed Processing with Applications, ISPA

作者： R. Aversa B. Di Martino M. Ficco S. Venticinque Department of Information Engineering Seconda Universita di Napoli Aversa Italy

Many contexts of every-day life are characterized by pervasiveness and ubiquity of embedded systems. These features can be exploited to support people in different scenarios, such as emergency situations and post disaster management. In this paper, we propose an agent-based approach to assist and simulate human critical activities in such scenarios. We propose a rule-based solution, which is implemented as a decentralized solution, which delegates the verification of rules to independent mobile agents. Agents are software components that interact with neighboring objects and react on the basis of the surrounding context. Moreover, a simulation tool is presented. It is used to model the remote scenario by collecting of context information from the field. It supports the on-line monitoring of the ongoing activities and the prediction of future situations. We present an implementation of the proposed solution to support and supervise human activities in real scenarios.

关键词： Context Bluetooth Temperature sensors Safety Radiofrequency identification software

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Conflict Avoidance Scheduling Using Grouping List for Transactional Memory

Conflict Avoidance Scheduling Using Grouping List for Transa...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Dongmin Choi Seung Hun Kim Won W. Ro Mobile Communication Division Samsung Electronics Limited Gumi Gyeongbuk South Korea School of Electrical and Electronic Engineering Yonsei University Seoul South Korea

Conventional Transactional Memory (TM) systems may experience performance degradation in applications with high contention, given the fact that execution of transaction will frequently restart due to conflicts. The restarting of transaction essentially requires rollback that is a wasteful operation. To address this point, we developed a system to reduce the overhead caused by high contention. In this paper, we present a method called Conflict Avoidance Scheduling (CAS), which prevents the conflicts in high contention by use of conflict characteristic. In CAS, threads that execute transactions which have high probability of conflicts are grouped together. Based on the group information, concurrent execution of threads in the same group is restricted. Therefore, threads that may cause conflict are serially executed. We evaluate the performance of the proposed design by comparing it with Log TM-SE. The simulation results show that our system improves the performance by 23% on an average in applications with high contention, as compared with the conventional Log TM-SE.

关键词： Registers Message systems Hardware Scheduling History Synchronization software

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The Research and Analysis of Hungarian Algorithm in the Structure Index Reduction for DAE

The Research and Analysis of Hungarian Algorithm in the Stru...

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The Eleventh international symposium on distributed Computing and Applications to Business,engineering and Science(DCABES2012)(第十一届分布式计算及其应用国际学术研讨会)(原名:电子商务、工程及科学领域的分布式计算和应用国际学术研讨会)

作者： Yan Zeng Xuesong Wu Jianwen Cao Laboratory of Parallel Software and Computational Science of Software Institute of Software Chinese Laboratory of Parallel Software and Computational Science of Software Institute of Software Chinese

Modeling of complex physical systems with Modelica usually leads to the high-index differential algebraic equation system(DAE),index reduction is an important part of solving the high-index *** structure index reduction algorithm is one of the popular methods,but in special cases,it *** relaxation algorithm can detect and correct the breakdown *** the maximum weight matching of bipartite graph is an important part of the combinatorial relaxation *** order to choose the proper method for the large-scale,dense bipartite graph,this paper provides three implementations of the Hungarian *** experiment results and the theory show that the BFS single-augmented method is better than others.

关键词： Modelica Bipartite Graph DAE Hungarian Algorithm Augmenting Path

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Real-Time Monitoring of Multicore SoCs through Specialized Hardware Agents on NoC Network Interfaces

Real-Time Monitoring of Multicore SoCs through Specialized H...

引用

IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： George Kornaros Dionisios Pnevmatikatos Applied Informatics & Multimedia Department Technological Educational Institute Estavromenos Heraklion Greece Electronics & Computer Engineering Department Technical University of Crete Kounoupidiana Chania Greece

Network-on-chip based multicore systems need efficient management of a multitude of processing resources, hence avoiding hardware and system software from making inefficient time- and power-decisions at runtime. Hardware event management is a necessary path to assist in high-speed management of captured events and enable efficient reaction mechanisms. This paper proposes different micro architecture alternatives and describes an infrastructure for real-time monitoring and management of network-on-chip based systems. High-speed and energy efficient circuit techniques are deployed for monitoring agents that reside at the network interfaces in order to be configured dynamically and communicate computed statistics to centralized hardware monitor managers of different functionality and complexity. An implementation of a pipelined centralized monitor manager is shown, with the capacity to maintain event ordering and process different types of concurrent events. A single event is served with a latency of seven clock cycles. The presented results of a quantitative evaluation provide guidelines for system-level designers, proving the need for flexible and at the same time efficient filters for real-time monitors inside complex NoC-based SoCs.

关键词： Monitoring Probes System-on-a-chip Hardware Nickel Multicore processing Vectors

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MapReduce across distributed Clusters for Data-intensive Applications

MapReduce across Distributed Clusters for Data-intensive App...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Lizhe Wang Jie Tao Holger Marten Achim Streit Samee U. Khan Joanna Kolodziej Dan Chen Center for Earth Observation and Digital Earth Chinese Academy of Sciences China Steinbuch Center for Computing Karlsruhe Institute of Technology Germany Department of Electrical and Computer Engineering North Dakota State University USA Department of Mathematics and Computer Science University of Bielsko-Biała Poland School of Computer China University of Geoscience China

Recently, the computational requirements for large scale data-intensive analysis of scientific data have grown significantly. In High Energy Physics (HEP) for example, the Large Hadron Collider (LHC) produced 13 petabytes of data in 2010. This huge amount of data are processed on more than 140 computing centers distributed across 34 countries. The MapReduce paradigm has emerged as a highly successful programming model for large-scale data-intensive computing applications. However, current MapReduce implementations are developed to operate on single cluster environments and cannot be leveraged for large-scale distributed data processing across multiple clusters. On the other hand, workflow systems are used for distributed data processing across data centers. It has been reported that the workflow paradigm has some limitations for distributed data processing, such as reliability and efficiency. In this paper, we present the design and implementation of GHadoop, a MapReduce framework that aims to enable large-scale distributed computing across multiple clusters. G-Hadoop uses the Gfarm file system as an underlying file system and executes MapReduce tasks across distributed clusters. Experiments of the G-Hadoop framework on distributed clusters show encouraging results.

关键词： Servers distributed databases Data processing Torque software Computer architecture Computational modeling

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Performance Modeling of Design Patterns for distributed Computation

Performance Modeling of Design Patterns for Distributed Comp...

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international symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems (MASCOTS)

作者： Ronald Strebelow Mirco Tribastone Christian Prehofer Fraunhofer Institute of Open Communication Systems (FOKUS) Munich Germany Department for Informatics Ludwig Maximilian Universität Munchen Germany

关键词： Message systems Monitoring Instruction sets Unified modeling language Object oriented modeling Sockets Computational modeling

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